Subject: Re: WG question: Accept draft-yang-forces-model-02.txt as WG doc?

From: "Yang, Lily L" <[email-masked]>
Date: Sun, 27 Jul 2003 15:09:03 -0700

Hi, Weiming --
Thanks for your comments. 
Regarding your comment #1) below, I think you are right that we didn't pay close attention to the intersected connectionin in Fig 3(a). What is funny was that at Vienna during the FE model discussion, some poeple including myself objected Zsolt&Steve's statement in their draft that "the model allows for connecting more than one LFB output to a single LFB input" but I guess I didn't realize that we are doing exactly that in our own draft!
I think we need to put a mux block there to connect the two outputs from two blocks into one input for classifier.
 
Thanks for catching this!
Lily

-----Original Message-----
From: Weiming Wang [mailto:[email-masked]]
Sent: Saturday, July 26, 2003 1:05 PM
To: [email-masked]
Subject: Re: WG question: Accept draft-yang-forces-model-02.txt as WG doc?

Dear David, and Lily, Joel, Ram, and Alan,

As one in the mailing list, I favor this model draft as WG document. This surely can speed up WG work and make research more focusing.
 
I'm interested in the model work, so I have made some comments on this document as follows, hoping to be of some help to perfect the document:
 
1. In Figure 3(a) shown bellow, connections between blocks seem in an intersected way,
 
                          +--------------------- 
                          |                                             
         +-----------+    |     +-----------+                          
         |           |    v     |           |                                 
       ->| ingress   |--------->|classifier |----
         | ports     |          |           |---- 
         +-----------+          +-----------+    
                                                                                                    
I don't know if intersected connections may make topology representation more complex or not. Actually the figure can also be expressed as follows, 
         
                          +--------------------- 
                          |                                             
         +-----------+    |     +-----------+                          
         |           |    +---->|           |                                 
       ->| ingress   |--------->|classifier |----
         | ports     |          |           |---- 
         +-----------+          +-----------+    
                                                                                                    
Although a classifier may only have one input in the hardware viewpoint, this is practical, because FE models are abstraced models from the ForCES viewpoint. For the above changed figure, we only need to properly set classifier attributes then it can surely get the packets and know where they are from. 
 
If intersected connections may make things complicated, can it be stated in the document to aoid using it?

---

From: Steven Blake <[email-masked]>
Date: Mon, 28 Jul 2003 12:22:58 -0400

On Sun, 2003-07-27 at 18:09, Yang, Lily L wrote:

> Regarding your comment #1) below, I think you are right that we didn't pay > close attention to the intersected connectionin in Fig 3(a). What is funny
> was that at Vienna during the FE model discussion, some poeple
> including myself objected Zsolt&Steve's statement in their draft that
> "the model allows for connecting more than one LFB output to a single
> LFB input" but I guess I didn't realize that we are doing exactly that
> in our own draft!
> I think we need to put a mux block there to connect the two outputs from
> two blocks into one input for classifier.
>

I don't understand what problem a mux block is supposed to solve.

Regards,

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Steven L. Blake               <[email-masked]>
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