Subject: Re: [RAM] Re: [Int-area] Please be more specific about the problem

From: Eliot Lear <[email-masked]>
Date: Thu, 22 Mar 2007 18:51:13 +0100

Noel,

An engineering problem has been raised, and while a new architecture can 
be a solution to an engineering problem, I want to understand just how 
far we have to go to fix the engineering problem.  In order to do that I 
have to understand the engineering problem better.  And so I wonder if 
someone can point me to the presentations that were given at the routing 
area so I can see what we're talking about.  Amazingly, in the seven or 
so presentations I've taken on this topic, only one of them had any data 
at all (thank you Tony & Vince) about routing growth, but even it did 
not answer this question:  is our primary concern control plane churn in 
the form of memory bandwidth or memory size?  I've gotten an oral answer 
of "both", but at least some data is needed in order to answer the 
question of what sort of characteristics any mapping from id to loc must 
have.  That was the point that I amongst others tried to make at the 
mike, today.

Which brings me to Bernard's point:

> a. Performance data is often highly dependent on the implementations being 
> studied, and therefore it is often unclear whether the conclusions hold 
> universally. 
>
> b. There are often multiple solutions available to the problem, some of 
> which will perform better than others in given use cases.  Without 
> agreement on the use cases, it can therefore be difficult to agree which 
> solutions are superior, even if the performance data itself is 
> unassailable (which is itself rare). 
Understood, and so if you can tell me what "the problem" is with some 
reason to believe so, I believe we will have gotten over this hurdle.  I 
believe therefore the questions I asked are not beyond the bounds of reason.

Eliot

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From: Tony Li <[email-masked]>
Date: Thu, 22 Mar 2007 19:15:24 +0100

Eliot,

> is our primary concern control plane churn in the form of memory  
> bandwidth or memory size?

My primary concern at this point is memory latency in the RIB.  You  
should be careful to note the difference between bandwidth and  
latency and it's impact on performance.

Tony