Subject: [Pce] F and S bit in draft-ietf-pce-segment-routing

From: "Chengli (Cheng Li)" <[email-masked]>
Date: Wed, 21 Aug 2019 03:22:30 +0000

Hi authors,

I am a little bit confusing of F and S bit in SR-ERO subobject.  https://tools.ietf.org/html/draft-ietf-pce-segment-routing-16#section-4.3.1

What is F standing for ?

and how about S ?  S for SID?

It seems like S and F bit can not be set at the same time, correct?

Thanks,
Cheng

---

From: Dhruv Dhody <[email-masked]>
Date: Wed, 21 Aug 2019 11:20:45 +0530

Hi Cheng,

Not an author, but as a document shepherd for this one -

The alphabets assigned to the bits do not have to expand to a keyword in the
description, even though that is the usual practice for readability purpose.
I am not sure why the authors picked "F" but it did not matter to me while
reviewing, what mattered was the description and usage of the bit.

Might be interesting to note that we have similar cases when you scan the flag
registries in our IANA page - https://www.iana.org/assignments/pcep/pcep.xhtml

And regarding setting of both flags, yes - that is not allowed and we have
this text -

   If a PCC receives an SR-ERO subobject in which the S and F bits are
   both set to 1 (that is, both the SID and NAI are absent), it MUST
   consider the entire ERO invalid and send a PCErr message with Error-
   Type = 10 ("Reception of an invalid object") and Error-Value = 6
   ("Both SID and NAI are absent in SR-ERO subobject").

I encourage authors to put forward their perspective.

Thanks!
Dhruv

On Wed, Aug 21, 2019 at 8:57 AM Chengli (Cheng Li) <[email-masked]> wrote:
> _______________________________________________
> Pce mailing list
> [email-masked]
> https://www.ietf.org/mailman/listinfo/pce