Subject: [NEXTEL-1] UniversalSoftwareRadioPeripheral (USRP)

From: [email-masked]
Date: Mon, 24 May 2004 00:08:59 -0400

The UniversalSoftwareRadioPeripheral (USRP) is a low-cost, high speed
implementation of GnuRadioHardware. It is currently being developed by a
team led by MattEttus.

There are many great Analog-to-Digital and Digital-to-Analog chips that
do exactly what we need, for pretty cheap. They would sit well on a
motherboard, but nobody puts them there. Nobody seems to have put them
into low cost general purpose computers or peripherals at all. (They
were probably waiting for someone to write some software like GnuRadio
that would use the hardware.) So EricBlossom, MattEttus and a few
GnuRadio contributors designed and built an interface that uses these
chips, and there's a manufacturer starting to make them.

We have produced small runs of two prototype versions, and the design is
close to final. Some of the Rev 0 prototypes are out in the field, being
used by various volunteers. The Rev 1 prototypes are still being brought
up. Rev 1 or something very close to it will be available for purchase
in 2004.

The Rev 1 USRP (pictured above) consists of a main board and up to four
daughter boards. It has the following features:
USB 2.0 interface (possibly fast enough for HdTv, and also does very
many other things). (Note that most USB 2.0 host interface chips only
support a fraction of the full specified USB 2.0 bandwidth. This device
can use it all, if the host supports it. We measured it running at
32Mbytes/sec to an IBM laptop.)

Requires a 5V external power wall-wart (it needs more and higher quality
power than USB provides)
4 High-Speed AD Converters (64 MS/s, 12-bit) to sample signals up to
about 200 MHz.

[[* *cough* this looks like a typo: 4 x 64 = 256 MS/s aggregate; that's
< 400+ MS/s (Nyquist criterion for 200 MHz without undersampling). Fix?
Explain? Explanation: You may bandpass-sample signals up to 200 MHz. Of
course the bandwidth of the signal of interest is limited by the Nyquist
criterion. *]]

4 High-Speed DA Converters (128 MS/s, 14-bit) to generate signals up to
about 50 MHz.  Altera FieldProgrammableGateArray for high bandwidth
math, and to reduce the data rates to something you can squirt over
USB2.
Lots of digital, serial, and low speed analog IO for controlling
daughterboards

2 Daughterboard slots hold any RF receiver interface or tuner

2 Daughterboard slots hold any RF transmitter

Daughterboards now in design or prototype include:

dual raw coax connection (SMA connectors to external tuners or signal
generators) dual 50-800 MHz RX, 8 MHz IF

bandwidth (Microtune 4702 cable modem tuners) 420 - 450 MHz amateur band
RX + TX (takes 1 RX + 1 TX slot)

902 - 928 MHz amateur band RX + TX (takes 1 RX + 1 TX slot)

1.24 - 1.30 GHz amateur band RX + TX (takes 1 RX + 1 TX slot)

2.30 - 2.45 GHz amateur band RX + TX (takes 1 RX + 1 TX slot)

See RfSections4USRP for daughterboard interface details or breadboarding

Possible PCI or PCI-X version later (for higher bus bandwidth)

USB bandwidth is our limiting factor. Our standard FPGA configuration
includes digital up and down converters implemented with CIC filters. We
can sustain 32MB/sec across the USB. The usual i/o format is 16-bit I
and 16-bit Q data (complex), resulting in 8M complex samples/sec across
the USB. This provides a maximum effective total spectral bandwidth of
about 6 MHz. Of course you can select much narrower ranges by changing
the decimation rate. In the fully loaded system, the FPGA implements up
to 4 digital up and 4 digital down converters. This allows 1, 2 or 4
separate channels to be extracted from the RF region tuned by the
daughterboard.

(The older Rev 0 prototypes are described at UsrpProtos and
UsrpProtoIntro.)
Everything (FPGA circuitry and USB Microcontroller) is programmable over
the USB2 bus. The FPGA contains digital up and down converters,
decimators, interpolators, and glue logic. Highly competent users will
be able to reprogram the FPGA to implement other functions too.

If a daughterboard is using real sampling (i.e. not quadrature), you
could attach as many as 4 receivers & antennas and 4 transmitters &
antennas to the USRP. Daughterboards can also be built to use Quadrature
sampling, which cuts those numbers in half, but gives better performance
in high bandwidth applications.

The device will perhaps be available in Q2 of 2004. We do not have final
retail pricing for either the USRP board or for any of the
daughterboards. We expect that the cheapest complete working setups will
be in the $550 range (single Rx and Tx, no enclosures). A fully loaded
system with 2 Tx and 2 Rx daughterboards, a nice enclosure and 1W of
output power may be in the $2000 range.

So far, there is no way to pre-order the device. However, we have been
able to send Rev 0 prototype boards to a few people who are improving
the GnuRadio software that runs the USRP. Once the Rev 1 boards are
fully working, a vendor will sell the final configuration over the web
and through their other sales channels. This page will tell you where to
get them, once that happens; and it will of course be posted to the
MailingList?.

All schematics and design files will be publicly available under a GNU
license.

Progress report - March 31, 2004
The USRP Rev 1 protos are back from the assembly house and are now being
tested! So far, so good! We can load firmware, fpga bitstreams, talk to
the ADC's and DAC's, and wiggle lines on the daughterboards. The
UsrpRev1? for details.

Progress report - February 9, 2004
The board turn for the new USRP that features daughterboards for the Rx
and Tx sections is now underway. For information on building RF
daughterboards, please see RfSections4USRP.

Progress report - December 12, 2003
There are now USRP Protos in the wild! See UsrpProtos for general
discussion of the prototypes and UsrpProtoIntro for the getting started
information including links to source code, schematics, etc.

Progress Report - November 7, 2003
The Rx path is now working! The FPGA to FX2 bus interface is sorted out,
as well as the problems with the digital down converter. Next thing to
sort out is our bandwidth across the USB. It looks like the user mode
usb driver is capable of queuing multiple asynchronous requests, so this
looks doable. Our problem is really related to inter-packet latency on
the USB; if the gaps are too big, the converters underrun. At this point
we've got the throughput turned down which allows us to make progress
regardless. The EHCI USB 2.0 host controller is capable of transmitting
16MB of data without CPU intervention, so it's just a matter of getting
the hardware to do what it's capable of.

We've also built some nice GUI stuff in Python using wxPython. See
PythonScopes.
Take a look at UsrpRxInAction to see examples of the USRP doing its
tricks along with explanations.

Progress Report - October 23, 2003
Transmission of a single channel of complex (I&Q) waveforms is working
pretty well. However, there are problems with the bandwidth and latency
through USB2 that limit the sample rate that we can support; it's
nowhere near 50MHz yet. The USB is currently being accessed via a user
mode process, rather than a kernel driver. We have C++ and Python code
that can transmit via the USRP. Transmitted signals are interpolated in
the FPGA into a 120Msamples/sec signal for the DAC.
Reception of data via USRP is starting to work. There are major
latency/bandwidth issues to be resolved. There are still unresolved
glitches in the samples even at low data rates, as well as problems when
downconverting in the USRP's FPGA.  There is simple C++ and Python code
for testing.

Progress Report - September 26, 2003
The board is able to transmit simple tones via DMA from the host, using
a Python script to control GNU Radio. A problem in the Cypress USB
interface chip slowed us down, but has now been debugged (after we got
Cypress to admit there was a bug).

Progress Report - August 26, 2003
We have code being loaded into the FPGA! It shouldn't be long now before
we have basic transmit and receive working

Progress Report - CCC Camp, August 7-10, 2003
MattEttus and EricBlossom brought a few prototype boards to Chaos
Computer Club Camp, showed them to attendees, and spoke about the
project.

At that time, the prototype boards could be powered-up and were able to
receive commands over the USB2 interface and transfer bytes in both
directions. Test firmware can be loaded into the USB microcontroller
over the USB interface. A few problems were found in the board layout,
which will be corrected in the production boards. By the end of the
event, the team had not yet succeeded at loading a circuit into the
FPGA. (This is required to generate the clocks for the analog-to-digital
converters.)

http://comsec.com/wiki?UniversalSoftwareRadioPeripheral

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