Subject: (no subject)

From: [email-masked]
Date: Fri, 11 Jul 2003 17:51:24 +0200

Hi,
I'm a newcomer to this discussion, and I would like to know whether
there have already been some discussions addressing the synchronization
issue, in an  asynchronous scenario as it is described in section 4.3.3 of
draft-ietf-pwe3-tdm-requirements-01?
My concern is related to the required processing to implement when
providing
 2Mbit/s E1 interface circuit emulation service.
Is there some means such as ATM AAL1 SRTS foreseen to answer to this issue?

Thanks in advance,
Regards,

Philippe.

Philippe DOL LO
ALCATEL
FND/E10 BU/R&D/HWCC
tel: +33 2 96 04 75 02
fax: +33 2 96 04 72 22
email: [email-masked]

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From: Sasha Vainshtein <[email-masked]>
Date: Fri, 11 Jul 2003 22:31:55 +0200

Philippe,
I suggest you to take a look at draft-vainshtein-cesopsn-06.txt.
This draft proposes usage of the standard RTP header as part of
the CES encapsulation layer, and - regarding your question -
defines two modes of generating timestams in this header:
- Absolute (default) - when the i/f line clock is used for
  the timestamping
- Differential - when a common synchronizationsource is accesssible
  at the two PEs terminating a TDM PW and is used for timestaming.
  This mode provides for at least the same functionality (and in
  the same scenarios)as SRTS in AAL1-based ATM CES.
Hopefully this helps.
----------------------------------------------------------------------------
--------
With best regards,
                          Sasha Vainshtein
email:   [email-masked] <mailto:[email-masked]> 
phone:  +972-3-7659993 (office)
            +972-8-9254948 (home)
            +972-58-674833 (cellular)

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> Subject: [PWE3] (no subject)
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> 
> Hi,
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---

From: "Yaakov Stein" <[email-masked]>
Date: Sun, 13 Jul 2003 10:09:29 +0300

> there have already been some discussions addressing the 
> synchronization issue, in an  asynchronous scenario as it is described in 
> section 4.3.3 of draft-ietf-pwe3-tdm-requirements-01?
> providing  2Mbit/s E1 interface circuit emulation service.

Your question needs to be answered in two parts.

In the usual case there is no common clock, available to both ingress and egress.
In this case some adaptive clock recovery must be performed.
There are numerous algorithms for this purpose,
and they CAN conform to internationally recognized jitter and wander constraints.

If a common clock is somehow available to both ingress and egress
(e.g. from GPS or from the physical layer of a single-hop optical link)
then RTP (for CESoPSN) or SRTS (for TDMoIP) may be used.
RTP provides a layer-4 timestamp,
while the SRTS provides a layer-2 residual timestamp.

Y(J)S