[^:]*: Assembler messages:
[^:]*:16: Error: bad type in SIMD instruction -- `vddup.s16 q0,r0,#1'
[^:]*:17: Error: bad type in SIMD instruction -- `vddup.u64 q0,r0,#1'
[^:]*:18: Error: immediate must be either 1, 2, 4 or 8 -- `vddup.u32 q0,r0,#3'
[^:]*:19: Error: immediate must be either 1, 2, 4 or 8 -- `vddup.u32 q0,r0,#0'
[^:]*:20: Error: bad type in SIMD instruction -- `vdwdup.s16 q0,r0,r1,#1'
[^:]*:21: Error: bad type in SIMD instruction -- `vdwdup.u64 q0,r0,r1,#1'
[^:]*:22: Error: immediate must be either 1, 2, 4 or 8 -- `vdwdup.u32 q0,r0,r1,#3'
[^:]*:23: Error: immediate must be either 1, 2, 4 or 8 -- `vdwdup.u32 q0,r0,r1,#0'
[^:]*:24: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:25: Error: r15 not allowed here -- `vdwdup.u32 q0,r0,pc,#1'
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:29: Error: syntax error -- `vddupeq.u32 q0,r0,#1'
[^:]*:30: Error: syntax error -- `vddupeq.u32 q0,r0,#1'
[^:]*:32: Error: syntax error -- `vddupeq.u32 q0,r0,#1'
[^:]*:33: Error: vector predicated instruction should be in VPT/VPST block -- `vddupt.u32 q0,r0,#1'
[^:]*:35: Error: instruction missing MVE vector predication code -- `vddup.u32 q0,r0,#1'
[^:]*:37: Error: syntax error -- `vdwdupeq.u32 q0,r0,r1,#1'
[^:]*:38: Error: syntax error -- `vdwdupeq.u32 q0,r0,r1,#1'
[^:]*:40: Error: syntax error -- `vdwdupeq.u32 q0,r0,r1,#1'
[^:]*:41: Error: vector predicated instruction should be in VPT/VPST block -- `vdwdupt.u32 q0,r0,r1,#1'
[^:]*:43: Error: instruction missing MVE vector predication code -- `vdwdup.u32 q0,r0,r1,#1'
