/*
 * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
 * SPDX-License-Identifier: MIT
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#ifndef __gb10b_dev_xtl_ep_pcfg_gpu_h__
#define __gb10b_dev_xtl_ep_pcfg_gpu_h__
/* This file is autogenerated.  Do not edit */
#define NV_EP_PCFG_GPU                                                                                         0xFFF:0x000          /* RW--D */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2                                                                   0x00000084           /* R--4R */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES                                                3:0                  /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_A_AND_B                                  0x00000003           /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_A                                        0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_B                                        0x00000002           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_B_AND_C                                  0x00000006           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_A_AND_B_AND_C                            0x00000007           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_B_AND_C_AND_D                            0x0000000E           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_A_AND_B_AND_C_AND_D                      0x0000000F           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_RANGE_NOT_SUPP                                 0x00000000           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_OVERRIDEABLE                                   1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE                                               4:4                  /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_SUPPORTED                                     0x00000001           /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_NOT_SUPPORTED                                 0x00000000           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_OVERRIDEABLE                                  1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ARI_FORWARDING                                                    5:5                  /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ARI_FORWARDING_NOT_SUPPORTED                                      0x00000000           /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ARI_FORWARDING_SUPPORTED                                          0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ARI_FORWARDING_OVERRIDEABLE                                       1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING                                                 6:6                  /* R-CVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING_NOT_SUPPORTED                                   0x00000000           /* R-C-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING_SUPPORTED                                       0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING_OVERRIDEABLE                                    1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT                                            7:7                  /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_NOT_SUPPORTED                              0x00000000           /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_SUPPORTED                                  0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_OVERRIDEABLE                               1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT                                            8:8                  /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_NOT_SUPPORTED                              0x00000000           /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_SUPPORTED                                  0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_OVERRIDEABLE                               1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT                                              9:9                  /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_NOT_SUPPORTED                                0x00000000           /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_SUPPORTED                                    0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_OVERRIDEABLE                                 1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING                                       10:10                /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING_NOT_SUPPORTED                         0x00000000           /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING_SUPPORTED                             0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING_OVERRIDEABLE                          1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LTR_MECHANISM                                                     11:11                /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LTR_MECHANISM_SUPPORTED                                           0x00000001           /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LTR_MECHANISM_NOT_SUPPORTED                                       0x00000000           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LTR_MECHANISM_OVERRIDEABLE                                        0                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_TPH_COMPLETER                                                     13:12                /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_TPH_COMPLETER_NOT_SUPPORTED                                       0x00000000           /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_TPH_COMPLETER_SUPPORTED                                           0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_TPH_COMPLETER_OVERRIDEABLE                                        1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LN_SYSTEM_CLS                                                     15:14                /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LN_SYSTEM_CLS_NOT_SUPPORTED                                       0x00000000           /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LN_SYSTEM_CLS_SUPPORTED                                           0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_LN_SYSTEM_CLS_OVERRIDEABLE                                        1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER                                              16:16                /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_SUPPORTED                                    0x00000001           /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_NOT_SUPPORTED                                0x00000000           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_OVERRIDEABLE                                 1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER                                              17:17                /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_SUPPORTED                                    0x00000001           /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_NOT_SUPPORTED                                0x00000000           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_OVERRIDEABLE                                 0                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF                                                              19:18                /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_MSG_SGNL                                                     0x00000001           /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_NOT_SUPPORTED                                                0x00000000           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_WAKE_SGNL                                                    0x00000002           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_MSG_WAKE_SGNL                                                0x00000003           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_OBFF_OVERRIDEABLE                                                 1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EXTENDED_FMT                                                      20:20                /* R-IVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EXTENDED_FMT_NOT_SUPPORTED                                        0x00000000           /* R-I-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EXTENDED_FMT_SUPPORTED                                            0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EXTENDED_FMT_OVERRIDEABLE                                         1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX                                                21:21                /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_NOT_SUPPORTED                                  0x00000000           /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_SUPPORTED                                      0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_OVERRIDEABLE                                   1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX                                            23:22                /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_4                                          0x00000000           /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_1                                          0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_2                                          0x00000002           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_3                                          0x00000003           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_OVERRIDEABLE                               1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION                                         25:24                /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_NOT_SUPPORTED                           0x00000000           /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_SUPPORTED_DSM                           0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_SUPPORTED_DSM_FF                        0x00000002           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_RESERVED                                0x00000003           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_OVERRIDEABLE                            1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_RED_INIT_REQ                                      26:26                /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_RED_INIT_REQ_NOT_SUPPORTED                        0x00000000           /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_RED_INIT_REQ_SUPPORTED                            0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_RED_INIT_REQ_OVERRIDEABLE                         1                    /*       */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_FRS                                                               31:31                /* R-EVF */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_FRS_NOT_SUPPORTED                                                 0x00000000           /* R-E-V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_FRS_SUPPORTED                                                     0x00000001           /* R---V */
#define NV_EP_PCFG_GPU_DEVICE_CAPABILITIES_2_FRS_OVERRIDEABLE                                                  1                    /*       */

#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC                                                                          0x000002B4           /* R--4R */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC__SAFETY                                                                  "parity"             /*       */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR                                                              15:0                 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR_INIT                                                         0x00000000           /* R-C-V */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR_OVERRIDEABLE                                                 0                    /*       */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS                                                                  22:16                /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS_INIT                                                             0x00000000           /* R-C-V */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS_OVERRIDEABLE                                                     0                    /*       */
#endif // __gb10b_dev_xtl_ep_pcfg_gpu_h__
