/*******************************************************************************
    Copyright (c) 2003-2016 NVIDIA Corporation

    Permission is hereby granted, free of charge, to any person obtaining a copy
    of this software and associated documentation files (the "Software"), to
    deal in the Software without restriction, including without limitation the
    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
    sell copies of the Software, and to permit persons to whom the Software is
    furnished to do so, subject to the following conditions:

    The above copyright notice and this permission notice shall be
    included in all copies or substantial portions of the Software.

    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
    DEALINGS IN THE SOFTWARE.

*******************************************************************************/


#ifndef __gr100_dev_fb_h__
#define __gr100_dev_fb_h__
/* This file is autogenerated.  Do not edit */
#define NV_PFB                                0x00100FFF:0x00100000 /* RW--D */
#define NV_PFB_FBIO_CALMASTER_CFG                                   0x00100700 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_CFG_PERIOD                                  15:0 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG_PERIOD_100MS                      0x000000A5 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG_PERIOD_15K                        0x00003A98 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG_INTERVAL                               23:16 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG_INTERVAL_10                       0x0000000A /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG_INTERVAL_48                       0x00000030 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG_DRVDLY                                 26:24 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG_DRVDLY_3                          0x00000003 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG_DRVDLY_5                          0x00000005 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG_DRVDLY_MAX                        0x00000007 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG_MAXDRIVE                               27:27 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG_MAXDRIVE_DISABLE                  0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG_MAXDRIVE_ENABLE                   0x00000001 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG_LIMIT_BW                               28:28 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_CFG_LIMIT_BW_DISABLE                  0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG_LIMIT_BW_ENABLE                   0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG_CLAMP_MIN                              29:29 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_CFG_CLAMP_MIN_DISABLE                 0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG_CLAMP_MIN_ENABLE                  0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG_CLAMP_MAX                              30:30 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_CFG_CLAMP_MAX_DISABLE                 0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG_CLAMP_MAX_ENABLE                  0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG_AUTOCOMP                               31:31 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_CFG_AUTOCOMP_DISABLE                  0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG_AUTOCOMP_ENABLE                   0x00000001 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CLAMP_MIN                             0x00100704 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_CLAMP_MIN_RISE                               6:0 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CLAMP_MIN_RISE_0                      0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CLAMP_MIN_FALL                              14:8 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CLAMP_MIN_FALL_0                      0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CLAMP_MIN_TERM                             22:16 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CLAMP_MIN_TERM_0                      0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CLAMP_MAX                             0x00100708 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_CLAMP_MAX_RISE                               6:0 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CLAMP_MAX_RISE_1F                     0x0000001F /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CLAMP_MAX_FALL                              14:8 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CLAMP_MAX_FALL_1F                     0x0000001F /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CLAMP_MAX_TERM                             22:16 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CLAMP_MAX_TERM_1F                     0x0000001F /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL                               0x0010070C /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_TEST_VAL                             6:0 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_TEST_VAL_0                    0x00000056 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_RISE_EN                              7:7 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_RISE_EN_ENABLE                0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_RISE_EN_DISABLE               0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_FALL_EN                              8:8 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_FALL_EN_ENABLE                0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_FALL_EN_DISABLE               0x00000001 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_TERM_EN                              9:9 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_TERM_EN_DISABLE               0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_TERM_EN_ENABLE                0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_TEST_VAL_EXT_DRIVE_DN                16:10 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_TEST_VAL_EXT_DRIVE_DN_INIT    0x0000004D /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_RISE_LOCK                          24:24 /* R-XVF */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_FALL_LOCK                          25:25 /* R-XVF */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_TERM_LOCK                          26:26 /* R-XVF */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_RISE_SLEW_LOCK                     27:27 /* R-XVF */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_FALL_SLEW_LOCK                     28:28 /* R-XVF */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_DQS_DLY                            29:29 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_DQS_DLY_THERMO                0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_DQS_DLY_DIRECT                0x00000001 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_MODE                               30:30 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_MODE_DRIVE                    0x00000001 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_MODE_SLEW                     0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_SELECT                             31:31 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_SELECT_HW                     0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SW_CTRL_SELECT_SW                     0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_RB                                    0x00100710 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_RB_RISE                                      6:0 /* R--VF */
#define NV_PFB_FBIO_CALMASTER_RB_FALL                                     14:8 /* R--VF */
#define NV_PFB_FBIO_CALMASTER_RB_TERM                                    22:16 /* R--VF */
#define NV_PFB_FBIO_CALMASTER_RB_CAL_CYCLE                               31:31 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_RB_CAL_CYCLE_DONE                     0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_RB_CAL_CYCLE_PENDING                  0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_RB_CAL_CYCLE_INIT                     0x00000001 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_RB_CAL_CYCLE_RESET                    0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_RB2                                   0x00100714 /* R--4R */
#define NV_PFB_FBIO_CALMASTER_RB2_RISE                                     6:0 /* R--VF */
#define NV_PFB_FBIO_CALMASTER_RB2_FALL                                    14:8 /* R--VF */
#define NV_PFB_FBIO_CALMASTER_RB3                                   0x00100760 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_RB3_RISE_FAIL_CNT                            7:0 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_RB3_RISE_FAIL_CNT_RST                 0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_RB3_RISE_PASS_CNT                           15:8 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_RB3_RISE_PASS_CNT_RST                 0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_RB3_FALL_FAIL_CNT                          23:16 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_RB3_FALL_FAIL_CNT_RST                 0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_RB3_FALL_PASS_CNT                          31:24 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_RB3_FALL_PASS_CNT_RST                 0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_RB4                                   0x00100764 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_RB4_TERM_FAIL_CNT                            7:0 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_RB4_TERM_FAIL_CNT_RST                 0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_RB4_TERM_PASS_CNT                           15:8 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_RB4_TERM_PASS_CNT_RST                 0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_RB5                                   0x00100768 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_RB5_RISE_FAIL_CNT                            7:0 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_RB5_RISE_FAIL_CNT_RST                 0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_RB5_RISE_PASS_CNT                           15:8 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_RB5_RISE_PASS_CNT_RST                 0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_RB5_FALL_FAIL_CNT                          23:16 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_RB5_FALL_FAIL_CNT_RST                 0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_RB5_FALL_PASS_CNT                          31:24 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_RB5_FALL_PASS_CNT_RST                 0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG                                  0x00100770 /* RW-4R */
#define NV_PFB_FBIO_CALGROUP_CFG_VDDP_MODE                               1:0 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG_VDDP_MODE_V1P5                   0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG_VDDP_MODE_V1P35                  0x00000002 /* RW--V */
#define NV_PFB_FBIO_CALGROUP_CFG_VDDP_MODE_V1P25                  0x00000003 /* RW--V */
#define NV_PFB_FBIO_CALGROUP_CFG_PU40_MODE                               2:2 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG_PU40_MODE_DISABLED               0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALGROUP_CFG_PU40_MODE_ENABLED                0x00000001 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG_COMP_CONFIG                             7:4 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG_COMP_CONFIG_INIT                 0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG_COMP_PU_CAL_SEL                       15:15 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG_COMP_PU_CAL_SEL_50PVREF          0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG_COMP_PU_CAL_SEL_VREFSEL          0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALGROUP_CFG_COMP_PD_CAL_SEL                       23:23 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG_COMP_PD_CAL_SEL_50PVREF          0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG_COMP_PD_CAL_SEL_VREFSEL          0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALGROUP_CFG_COMP_TERM_CAL_SEL                     31:31 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG_COMP_TERM_CAL_SEL_50PVREF        0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG_COMP_TERM_CAL_SEL_VREFSEL        0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALGROUP_CFG2                                 0x00100774 /* RW-4R */
#define NV_PFB_FBIO_CALGROUP_CFG2_TEST_EN                                0:0 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG2_TEST_EN_ENABLE                  0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALGROUP_CFG2_TEST_EN_DISABLE                 0x00000001 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG2_TEST_OUT_SEL                           7:4 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG2_TEST_OUT_SEL_0                  0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG2_TEST_CONFIG                          19:16 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG2_TEST_CONFIG_0                   0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG2_TEST_PWRD                            28:28 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG2_TEST_PWRD_DISABLED              0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALGROUP_CFG2_TEST_PWRD_ENABLED               0x00000001 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN                        0x00100778 /* RW-4R */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VAUXP                  2:0 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VAUXP_0         0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VAUXP_INIT      0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VCLAMP                 6:4 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VCLAMP_0        0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VCLAMP_INIT     0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VAUXC                 10:8 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VAUXC_0         0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VAUXC_INIT      0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VAUXP_LOAD              14:12 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VAUXP_LOAD_0       0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VAUXP_LOAD_INIT    0x00000001 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VAUXC_LOAD              22:20 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VAUXC_LOAD_0       0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VAUXC_LOAD_INIT    0x00000001 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_SPARE                   25:24 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_SPARE_INIT         0x00000002 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTTGEN_PWRD                 31:31 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTTGEN_PWRD_INIT       0x00000001 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR                            0x00100718 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR_ADR                               3:0 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR_ADR_4                      0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR_ADR_SUBP                        19:16 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR_ADR_SUBP_4                 0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR_ADR_CS                          27:24 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR_ADR_CS_4                   0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR2                           0x0010071C /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR2_DQS                              3:0 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR2_DQS_4                     0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR2_DAT                             11:8 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR2_DAT_4                     0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF                            0x00100720 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF_ADR                               3:0 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF_ADR_4                      0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF_ADR_SUBP                        19:16 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF_ADR_SUBP_4                 0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF_ADR_CS                          27:24 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF_ADR_CS_4                   0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF2                           0x00100724 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF2_DQS                              3:0 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF2_DQS_4                     0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF2_DAT                             11:8 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF2_DAT_4                     0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVT                            0x00100728 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVT_DQS                               3:0 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVT_DQS_4                      0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVT_DAT                              11:8 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_DRVT_DAT_4                      0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_SLWR                            0x0010072C /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_SLOPE_SLWR_ADR                               3:0 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_SLWR_ADR_4                      0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_SLWR_DQS                             27:24 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_SLWR_DQS_4                      0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_SLWF                            0x00100730 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_SLOPE_SLWF_ADR                               3:0 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_SLWF_ADR_4                      0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_SLOPE_SLWF_DQS                             27:24 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_SLOPE_SLWF_DQS_4                      0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR                           0x00100734 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR_ADR                              6:0 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR_ADR_0                     0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR_ADR_SUBP                       22:16 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR_ADR_SUBP_0                0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR_ADR_CS                         30:24 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR_ADR_CS_0                  0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR2                          0x00100738 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR2_DQS                             6:0 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR2_DQS_0                    0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR2_DAT                            14:8 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR2_DAT_0                    0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF                           0x0010073C /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF_ADR                              6:0 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF_ADR_0                     0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF_ADR_SUBP                       22:16 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF_ADR_SUBP_0                0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF_ADR_CS                         30:24 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF_ADR_CS_0                  0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF2                          0x00100740 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF2_DQS                             6:0 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF2_DQS_0                    0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF2_DAT                            14:8 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF2_DAT_0                    0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVT                           0x00100744 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVT_DQS                              6:0 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVT_DQS_4                     0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVT_DAT                             14:8 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_DRVT_DAT_4                     0x00000004 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_SLWR                           0x00100748 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_OFFSET_SLWR_ADR                              6:0 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_SLWR_ADR_0                     0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_SLWR_DQS                            30:24 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_SLWR_DQS_0                     0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_SLWF                           0x0010074C /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_OFFSET_SLWF_ADR                              6:0 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_SLWF_ADR_0                     0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_OFFSET_SLWF_DQS                            30:24 /* RWISF */
#define NV_PFB_FBIO_CALMASTER_OFFSET_SLWF_DQS_0                     0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG2                                  0x00100750 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_CFG2_TERM                                    0:0 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG2_TERM_DISABLE                     0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG2_TERM_ENABLE                      0x00000001 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG2_TRIGGER_CAL_CYCLE                       3:3 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_CFG2_TRIGGER_CAL_CYCLE_INACTIVE       0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG2_TRIGGER_CAL_CYCLE_ENABLED        0x00000001 /* -W--T */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_AUTO                       4:4 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_AUTO_ENABLED        0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_AUTO_DISABLED       0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_MODE                       5:5 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_MODE_PER_CYCLE      0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_MODE_PER_STEP       0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_RX_PWRD                            1:1 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_RX_PWRD_DISABLE             0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_RX_PWRD_ENABLE              0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_INT_PWRD                           2:2 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_INT_PWRD_INIT               0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_EXT_PWRD                           7:7 /* RWIVF */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_EXT_PWRD_INIT               0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_ENABLE                     6:6 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_ENABLE_OFF          0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_ENABLE_ON           0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG2_SAMPLE_COUNT                           11:8 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG2_SAMPLE_COUNT_INIT                0x00000005 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG2_SAMPLE_COUNT_MAX                 0x0000000F /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG2_LOCK_COUNT                            15:12 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG2_LOCK_COUNT_INIT                  0x00000005 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG2_LOCK_COUNT_MAX                   0x0000000F /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_DLY                      31:16 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_DLY_1024            0x00000400 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG3                                  0x00100754 /* RW-4R */
#define NV_PFB_FBIO_CALMASTER_CFG3_HBM_COMP                                0:0 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG3_HBM_COMP_ENABLE                  0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG3_HBM_COMP_DISABLE                 0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG3_HBM_SLWR_EN                             1:1 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG3_HBM_SLWR_EN_ENABLE               0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG3_HBM_SLWR_EN_DISABLE              0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG3_HBM_SLWF_EN                             2:2 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG3_HBM_SLWF_EN_ENABLE               0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG3_HBM_SLWF_EN_DISABLE              0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL                   4:3 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_0          0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_1          0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_2          0x00000002 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_3          0x00000003 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG3_TERM_MODE                               5:5 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG3_TERM_MODE_UP                     0x00000001 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG3_TERM_MODE_DN                     0x00000000 /* RW--V */
#define NV_PFB_FBIO_CALMASTER_CFG3_RISE_START_VAL                         14:8 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG3_RISE_START_VAL_INIT              0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG3_FALL_START_VAL                        22:16 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG3_FALL_START_VAL_INIT              0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALMASTER_CFG3_TERM_START_VAL                        30:24 /* RWIUF */
#define NV_PFB_FBIO_CALMASTER_CFG3_TERM_START_VAL_INIT              0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG3                                 0x00100758 /* RW-4R */
#define NV_PFB_FBIO_CALGROUP_CFG3_IREF_PWRD                              0:0 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG3_IREF_PWRD_ENABLE                0x00000001 /* RW--V */
#define NV_PFB_FBIO_CALGROUP_CFG3_IREF_PWRD_DISABLE               0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG3_ISOURCE_CTRL                           3:2 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG3_ISOURCE_CTRL_INIT               0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXP_LIMITER                     10:8 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXP_LIMITER_INIT          0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXC_LIMITER                    14:12 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXC_LIMITER_INIT          0x00000000 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXP_BW                         19:16 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXP_BW_INIT               0x0000000A /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXC_BW                         23:20 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXC_BW_INIT               0x0000000A /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXP_SRBOOST                    26:24 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXP_SRBOOST_INIT          0x00000006 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXC_SRBOOST                    30:28 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXC_SRBOOST_INIT          0x00000006 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG4                                 0x0010075C /* RW-4R */
#define NV_PFB_FBIO_CALGROUP_CFG4_COMP_PU_VREFP_CODE                     6:0 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG4_COMP_PU_VREFP_CODE_50PVREF      0x00000020 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG4_COMP_PD_VREFP_CODE                    14:8 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG4_COMP_PD_VREFP_CODE_50PVREF      0x00000020 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG4_COMP_TERM_VREFP_CODE                 22:16 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG4_COMP_TERM_VREFP_CODE_50PVREF    0x00000020 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG4_TEST_VREFP_CODE                      30:24 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG4_TEST_VREFP_CODE_50PVREF         0x00000020 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG5                                 0x0010077C /* RW-4R */
#define NV_PFB_FBIO_CALGROUP_CFG5_COMP_PU_VREFN_CODE                     5:0 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG5_COMP_PU_VREFN_CODE_50PVREF      0x00000020 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG5_COMP_PD_VREFN_CODE                    13:8 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG5_COMP_PD_VREFN_CODE_50PVREF      0x00000020 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG5_COMP_TERM_VREFN_CODE                 21:16 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG5_COMP_TERM_VREFN_CODE_50PVREF    0x00000020 /* RWI-V */
#define NV_PFB_FBIO_CALGROUP_CFG5_TEST_VREFN_CODE                      29:24 /* RWIVF */
#define NV_PFB_FBIO_CALGROUP_CFG5_TEST_VREFN_CODE_50PVREF         0x00000020 /* RWI-V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK                                      0x001FA3DC /* RW-4R */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_PMU_ENABLED_FUSE1  0x0000884E /* RW--V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK                                      0x001FA7C0 /* RW-4R */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_PMU_FECS_ENABLED_FUSE1  0x0000885E /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK                                      0x001FA7D0 /* RW-4R */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8   /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_PMU_ENABLED_FUSE1  0x0000884E /* RW--V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK                                      0x001FA7CC /* RW-4R */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK                                      0x001FA7C8 /* RW-4R */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_PMU_ENABLED_FUSE1  0x0000884E /* RW--V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK                                      0x001FA7C4 /* RW-4R */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_PMU_ENABLED_FUSE1  0x0000884E /* RW--V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK                                                      0x001FA9A8 /* RW-4R */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION                                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED                   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED                  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                                      0:0 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE                        0x00000001 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE                       0x00000000 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                                      1:1 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE                        0x00000001 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE                       0x00000000 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                                      2:2 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE                        0x00000001 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE                       0x00000000 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                                      3:3 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE                        0x00000001 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE                       0x00000000 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION                                           7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  15 /* RWE-V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED                  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED                 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                                     4:4 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE                       0x00000001 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE                      0x00000000 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                                     5:5 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE                       0x00000001 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE                      0x00000000 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                                     6:6 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE                       0x00000001 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE                      0x00000000 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                                     7:7 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE                       0x00000001 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE                      0x00000000 /*       */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_VIOLATION                                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR                          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON                            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION                                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR                         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON                           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED                          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED                          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED                         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED                         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE                                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_HSHUB_CONNECTION_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED                    0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK                                      0x001FA838 /* RW-4R */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FSP_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK                                      0x001FA7D4 /* RW-4R */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK                                      0x001FA7D8 /* RW-4R */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK                                      0x001FA7DC /* RW-4R */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK                                          0x001FA7E0 /* RW-4R */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK                                      0x001FA7E4 /* RW-4R */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK                                      0x001FA8E0 /* RW-4R */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_ESC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK                                      0x001FA7E8 /* RW-4R */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK                                      0x001FA7EC /* RW-4R */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK                                      0x001FA7F0 /* RW-4R */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK                                      0x001FA7F4 /* RW-4R */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK                                      0x001FA7F8 /* RW-4R */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK                                      0x001FA9A0 /* RW-4R */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_CONFIDENTIAL_COMPUTING_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK                                                      0x001FA9A4 /* RW-4R */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION                                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED                   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED                  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                                      0:0 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE                        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE                       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                                      1:1 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE                        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE                       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                                      2:2 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE                        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE                       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                                      3:3 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE                        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE                       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION                                           7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL                        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED                  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED                 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                                     4:4 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE                       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE                      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                                     5:5 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE                       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE                      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                                     6:6 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE                       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE                      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                                     7:7 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE                       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE                      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_VIOLATION                                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR                          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON                            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION                                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR                         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON                           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED                          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED                          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED                         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED                         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE                                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL       "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0              0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1             0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK                                          0x001F8F40 /* RW-4R */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK                                          0x001F8F44 /* RW-4R */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK                                      0x001F8EDC     /* RW-4R */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL         "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0  15 /* RWE-V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1  8     /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  15 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK                                      0x001FAA70 /* RW-4R */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  15 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK                                      0x001FAA74 /* RW-4R */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  15 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK                                               0x001FA5DC /* RW-4R */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION                                  3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED        0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED       0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                           0:0 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE             0x00000001 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE            0x00000000 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                           1:1 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE             0x00000001 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE            0x00000000 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                           2:2 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE             0x00000001 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE            0x00000000 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                           3:3 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE             0x00000001 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE            0x00000000 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION                                 7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  15 /* RWE-V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED       0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED      0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                          4:4 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE            0x00000001 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE           0x00000000 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                          5:5 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE            0x00000001 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE           0x00000000 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                          6:6 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE            0x00000001 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE           0x00000000 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                          7:7 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE            0x00000001 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE           0x00000000 /*       */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_VIOLATION                                   8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR               0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON                 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_VIOLATION                                  9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR              0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON                0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                            10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED               0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                           11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED              0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED              0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_SOURCE_ENABLE                                  31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_BIND_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED         0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK                                      0x001FAA48 /* RW-4R */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  15 /* RWE-V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED    0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK                                      0x001FAA4C /* RW-4R */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  15 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED    0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK                                      0x001FAA50 /* RW-4R */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  15 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED    0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_CTRL                                     0x001FA3A4 /* RW-4R */
#define NV_PFB_PRI_MMU_TLB_CTRL_L2_SIZE                                    1:0 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_CTRL_L2_SIZE_INIT                        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_CTRL_L2_FA_SIZE                                 3:2 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_CTRL_L2_FA_SIZE_INIT                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_CTRL_L2_RB_SIZE                                 5:4 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_CTRL_L2_RB_SIZE_INIT                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_CTRL_HUB_SIZE                                   7:6 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_CTRL_HUB_SIZE_INIT                       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_CTRL_HUB_FA_SIZE                                9:8 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_CTRL_HUB_FA_SIZE_INIT                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_CTRL_HUB_RB_SIZE                              11:10 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_CTRL_HUB_RB_SIZE_INIT                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_CTRL_FILL_SIZE_PTE                            13:12 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_CTRL_FILL_SIZE_PTE_INIT                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_CTRL_FILL_SIZE_PDE                            15:14 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_CTRL_FILL_SIZE_PDE_INIT                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_CTRL_FILL_SIZE_RB                             17:16 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_CTRL_FILL_SIZE_RB_INIT                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_CTRL_L2_SET_INDEX_BIG_PG                      19:18 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_CTRL_L2_SET_INDEX_BIG_PG_INIT            0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_CTRL_HUB_SET_INDEX_BIG_PG                     21:20 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_CTRL_HUB_SET_INDEX_BIG_PG_INIT           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_CTRL_L2_SET_INDEX_SMALL_PG                    23:22 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_CTRL_L2_SET_INDEX_SMALL_PG_INIT          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_CTRL_HUB_SET_INDEX_SMALL_PG                   25:24 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_CTRL_HUB_SET_INDEX_SMALL_PG_INIT         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_CTRL_ADDITIONAL_GPCMMUS_PER_CPC               29:28 /* R--VF */
#define NV_PFB_PRI_MMU_TLB_CTRL_ADDITIONAL_GPCMMUS_PER_GPC               31:30 /* R--VF */
#define NV_PFB_PRI_MMU_RSRVD                                        0x001FA3A8 /* RW-4R */
#define NV_PFB_PRI_MMU_RSRVD_FILL_PTE_CL_VC_B                              2:0 /* RWEVF */
#define NV_PFB_PRI_MMU_RSRVD_FILL_PTE_CL_VC_B_INIT                  0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_RSRVD_FILL_PTE_CL_VC_NB                             5:3 /* RWEVF */
#define NV_PFB_PRI_MMU_RSRVD_FILL_PTE_CL_VC_NB_INIT                 0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_RSRVD_FILL_RB_VC_B                                  8:6 /* RWEVF */
#define NV_PFB_PRI_MMU_RSRVD_FILL_RB_VC_B_INIT                      0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_RSRVD_FILL_RB_VC_NB                                11:9 /* RWEVF */
#define NV_PFB_PRI_MMU_RSRVD_FILL_RB_VC_NB_INIT                     0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_RSRVD_HUBTLB_CL_VC_B                              14:12 /* RWEVF */
#define NV_PFB_PRI_MMU_RSRVD_HUBTLB_CL_VC_B_INIT                    0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_RSRVD_HUBTLB_CL_VC_NB                             17:15 /* RWEVF */
#define NV_PFB_PRI_MMU_RSRVD_HUBTLB_CL_VC_NB_INIT                   0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_RSRVD_HUBTLB_RB_VC_B                              20:18 /* RWEVF */
#define NV_PFB_PRI_MMU_RSRVD_HUBTLB_RB_VC_B_INIT                    0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_RSRVD_HUBTLB_RB_VC_NB                             23:21 /* RWEVF */
#define NV_PFB_PRI_MMU_RSRVD_HUBTLB_RB_VC_NB_INIT                   0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_RSRVD_FAST_BIG_PG_FAULT_DISABLE                   26:26 /* R-EVF */
#define NV_PFB_PRI_MMU_RSRVD_FAST_BIG_PG_FAULT_DISABLE_TRUE         0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_RSRVD_FAST_BIG_PG_FAULT_DISABLE_FALSE        0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_RSRVD_HUBTLB_FAST_PATH_DISABLE                    28:28 /* RWEVF */
#define NV_PFB_PRI_MMU_RSRVD_HUBTLB_FAST_PATH_DISABLE_FALSE         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_RSRVD_HUBTLB_FAST_PATH_DISABLE_TRUE          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_RSRVD_L2TLB_FAST_PATH_DISABLE                     29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_RSRVD_L2TLB_FAST_PATH_DISABLE_FALSE          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_RSRVD_L2TLB_FAST_PATH_DISABLE_TRUE           0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_RSRVD_FILL_FAST_PATH_DISABLE                      30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_RSRVD_FILL_FAST_PATH_DISABLE_FALSE           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_RSRVD_FILL_FAST_PATH_DISABLE_TRUE            0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_RSRVD_IGNORE_INVALIDATES                          31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_RSRVD_IGNORE_INVALIDATES_FALSE               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_RSRVD_IGNORE_INVALIDATES_TRUE                0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_TLB_MISC                                         0x001FA3D0 /* RW-4R */
#define NV_PFB_PRI_MMU_TLB_MISC_L2_UF                                      2:0 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_MISC_L2_UF_INIT                          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_MISC_HUBTLB_UF_VC_B                             5:3 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_MISC_HUBTLB_UF_VC_B_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_MISC_HUBTLB_UF_VC_NB                            8:6 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_MISC_HUBTLB_UF_VC_NB_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_MISC_FILL_PTE_UF_VC_B                          11:9 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_MISC_FILL_PTE_UF_VC_B_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_TLB_MISC_FILL_PTE_UF_VC_NB                        14:12 /* RWEVF */
#define NV_PFB_PRI_MMU_TLB_MISC_FILL_PTE_UF_VC_NB_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL                              0x001FA3F8 /* RW-4R */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL__PRIV_LEVEL_MASK  0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER                          1:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_ALL          0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_NONE         0x00000003 /* RWE-V */
#define NV_PFB_PRI_MMU_BIND_IMB                                     0x001FA3AC /* RW-4R */
#define NV_PFB_PRI_MMU_BIND_IMB__PRIV_LEVEL_MASK  0x001FA5DC /*       */
#define NV_PFB_PRI_MMU_BIND_IMB_APERTURE                                   1:0 /* RWXVF */
#define NV_PFB_PRI_MMU_BIND_IMB_APERTURE_VID_MEM                    0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_IMB_APERTURE_INVALID                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_IMB_APERTURE_SYS_MEM_C                  0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_IMB_APERTURE_SYS_MEM_NC                 0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_IMB_VOL                                        2:2 /* RWXVF */
#define NV_PFB_PRI_MMU_BIND_IMB_VOL_FALSE                           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_IMB_VOL_TRUE                            0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_IMB_ADDR                                      31:4 /* RWXVF */
#define NV_PFB_PRI_MMU_BIND_IMB_ADDR_ALIGNMENT                      0x0000000c /*       */
#define NV_PFB_PRI_MMU_BIND                                         0x001FA3B0 /* RW-4R */
#define NV_PFB_PRI_MMU_BIND__PRIV_LEVEL_MASK  0x001FA5DC /*       */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID                                      8:0 /* RWEVF */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_INIT                          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_GRAPHICS                      384 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_RESERVED                      0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_DISPLAY                       0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_GSP                           0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_FLA                           0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_BAR1                          256 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_BAR2                          320 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_PMU                           0x00000005 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_SEC                           0x00000006 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_FSP                           0x00000007 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_PM                            0x0000000a /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_PM0                           0x0000000a /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_PM1                           0x0000000b /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_PM2                           0x0000000c /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_PM3                           0x0000000d /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_PM4                           0x0000000e /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_PM5                           0x0000000f /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_PM6                           0x00000010 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_PM7                           0x00000011 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_PM8                           0x00000012 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_PM9                           0x00000013 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVDEC                         0x0000001c /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVDEC0                        0x0000001c /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVDEC1                        0x0000001d /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVDEC2                        0x0000001e /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVDEC3                        0x0000001f /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVDEC4                        0x00000020 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVDEC5                        0x00000021 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVDEC6                        0x00000022 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVDEC7                        0x00000023 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVJPG                         0x00000024 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVJPG0                        0x00000024 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVJPG1                        0x00000025 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVJPG2                        0x00000026 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVJPG3                        0x00000027 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVJPG4                        0x00000028 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVJPG5                        0x00000029 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVJPG6                        0x0000002a /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVJPG7                        0x0000002b /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVENC                         0x0000002c /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVENC0                        0x0000002c /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVENC1                        0x0000002d /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVENC2                        0x0000002e /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE0                           0x00000041 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE1                           0x00000042 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE2                           0x00000043 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE3                           0x00000044 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE4                           0x00000045 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE5                           0x00000046 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE6                           0x00000047 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE7                           0x00000048 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE8                           0x00000049 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE9                           0x0000004a /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE10                          0x0000004b /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE11                          0x0000004c /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE12                          0x0000004d /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE13                          0x0000004e /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE14                          0x0000004f /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE15                          0x00000050 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE16                          0x00000051 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE17                          0x00000052 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE18                          0x00000053 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE19                          0x00000054 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_OFA0                          48 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST0                         0x00000055 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST1                         0x00000056 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST2                         0x00000057 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST3                         0x00000058 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST4                         0x00000059 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST5                         0x0000005a /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST6                         0x0000005b /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST7                         0x0000005c /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST8                         0x0000005d /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST9                         0x0000005e /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST10                        0x0000005f /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST11                        0x00000060 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST12                        0x00000061 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST13                        0x00000062 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST14                        0x00000063 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST15                        0x00000064 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST16                        0x00000065 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST17                        0x00000066 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST18                        0x00000067 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST19                        0x00000068 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST20                        0x00000069 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST21                        0x0000006a /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST22                        0x0000006b /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST23                        0x0000006c /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST24                        0x0000006d /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST25                        0x0000006e /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST26                        0x0000006f /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST27                        0x00000070 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST28                        0x00000071 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST29                        0x00000072 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST30                        0x00000073 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST31                        0x00000074 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST32                        0x00000075 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST33                        0x00000076 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST34                        0x00000077 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST35                        0x00000078 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST36                        0x00000079 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST37                        0x0000007a /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST38                        0x0000007b /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST39                        0x0000007c /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST40                        0x0000007d /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST41                        0x0000007e /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST42                        0x0000007f /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST43                        0x00000080 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST44                        0x00000081 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID0                         0x00000180 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID1                         0x00000181 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID2                         0x00000182 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID3                         0x00000183 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID4                         0x00000184 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID5                         0x00000185 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID6                         0x00000186 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID7                         0x00000187 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID8                         0x00000188 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID9                         0x00000189 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID10                        0x0000018a /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID11                        0x0000018b /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID12                        0x0000018c /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID13                        0x0000018d /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID14                        0x0000018e /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID15                        0x0000018f /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID16                        0x00000190 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID17                        0x00000191 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID18                        0x00000192 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID19                        0x00000193 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID20                        0x00000194 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID21                        0x00000195 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID22                        0x00000196 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID23                        0x00000197 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID24                        0x00000198 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID25                        0x00000199 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID26                        0x0000019a /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID27                        0x0000019b /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID28                        0x0000019c /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID29                        0x0000019d /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID30                        0x0000019e /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID31                        0x0000019f /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID32                        0x000001a0 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID33                        0x000001a1 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID34                        0x000001a2 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID35                        0x000001a3 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID36                        0x000001a4 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID37                        0x000001a5 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID38                        0x000001a6 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID39                        0x000001a7 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID40                        0x000001a8 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID41                        0x000001a9 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID42                        0x000001aa /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID43                        0x000001ab /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID44                        0x000001ac /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID45                        0x000001ad /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID46                        0x000001ae /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID47                        0x000001af /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID48                        0x000001b0 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID49                        0x000001b1 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID50                        0x000001b2 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID51                        0x000001b3 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID52                        0x000001b4 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID53                        0x000001b5 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID54                        0x000001b6 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID55                        0x000001b7 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID56                        0x000001b8 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID57                        0x000001b9 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID58                        0x000001ba /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID59                        0x000001bb /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID60                        0x000001bc /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID61                        0x000001bd /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID62                        0x000001be /* RW--V */
#define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID63                        0x000001bf /* RW--V */
#define NV_PFB_PRI_MMU_BIND_UPPER_IMB_ADDR                               29:12 /* RWEVF */
#define NV_PFB_PRI_MMU_BIND_UPPER_IMB_ADDR_INIT                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_BIND_UNBIND_TYPE                                  30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_BIND_UNBIND_TYPE_ALL                         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_BIND_UNBIND_TYPE_SMC_LOCAL                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_TRIGGER                                      31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_BIND_TRIGGER_FALSE                           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_BIND_TRIGGER_TRUE                            0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_BIND_EXT                                     0x001FA5D8 /* RW-4R */
#define NV_PFB_PRI_MMU_BIND_EXT__PRIV_LEVEL_MASK  0x001FA5DC /*       */
#define NV_PFB_PRI_MMU_BIND_EXT_GFID                                       5:0 /* RWEVF */
#define NV_PFB_PRI_MMU_BIND_EXT_GFID_INIT                           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_BIND_EXT_SMC_ID                                   30:28 /* RWEVF */
#define NV_PFB_PRI_MMU_BIND_EXT_SMC_ID_INIT                         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VADDR                             0x001FA3B4 /* RW-4R */
#define NV_PFB_PRI_MMU_INVALIDATE_VADDR__PRIV_LEVEL_MASK  0x001FAA74 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_VADDR_BITS                              31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VADDR_BITS_INIT                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VADDR_ALIGNMENT                   0x0000000c /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR                       0x001FA3E8 /* RW-4R */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR__PRIV_LEVEL_MASK  0x001FAA74 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_BITS                        19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_BITS_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB                               0x001FA3B8 /* RW-4R */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB__PRIV_LEVEL_MASK  0x001FAA74 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE                             1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM              0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_SYS_MEM              0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR                                31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR_INIT                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR_ALIGNMENT                0x0000000c /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB                         0x001FA3EC /* RW-4R */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB__PRIV_LEVEL_MASK  0x001FAA74 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_ADDR                          19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_ADDR_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_PASID                               0x001FA564 /* RW-4R */
#define NV_PFB_PRI_MMU_INVALIDATE_PASID__PRIV_LEVEL_MASK 0x001FAA74 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PASID_VAL                                 19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PASID_VAL_INIT                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_SIZE                                0x001FA568 /* RW-4R */
#define NV_PFB_PRI_MMU_INVALIDATE_SIZE__PRIV_LEVEL_MASK  0x001FAA74 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VAL                                   5:0 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VAL_INIT                       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_SIZE_GFID                                31:26 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_SIZE_GFID_INIT                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE                                   0x001FA3BC /* RW-4R */
#define NV_PFB_PRI_MMU_INVALIDATE__PRIV_LEVEL_MASK  0x001FAA74 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA                                   0:0 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_FALSE                      0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_TRUE                       0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB                                  1:1 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_FALSE                     0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_TRUE                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY                              2:2 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_FALSE                 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_TRUE                  0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY                                   5:3 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_NONE                       0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START_ACK_ALL              0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED            0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL              0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL           0x00000005 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR                              6:6 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_FALSE                 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_TRUE                  0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ACK                                     8:7 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_ACK_NONE_REQUIRED                0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ACK_INTRANODE                    0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_ACK_GLOBALLY                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_ID                       14:9 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_GPC_ID                         19:15 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_INVAL_SCOPE                           16:15 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_INVAL_SCOPE_ALL_TLBS             0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_INVAL_SCOPE_LINK_TLBS            0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS        0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE                    20:20 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_HUB           0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_USE_PASID                             21:21 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_USE_PASID_FALSE                  0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_USE_PASID_TRUE                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_USE_SIZE                              22:22 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_USE_SIZE_FALSE                   0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_USE_SIZE_TRUE                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PROP_FLUSH                            23:23 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PROP_FLUSH_FALSE                 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_PROP_FLUSH_TRUE                  0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL                           26:24 /* RWXVF */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_ALL                  0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_PTE_ONLY             0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE0           0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE1           0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE2           0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE3           0x00000005 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE4           0x00000006 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE5           0x00000007 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_READ          0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE         0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_STRONG 0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_RSVRVD        0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_WEAK   0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_ALL    0x00000005 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE_AND_ATOMIC 0x00000006 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ALL           0x00000007 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER                                31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_FALSE                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_TRUE                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_MAX_CACHELINE_SIZE                0x00000010 /*       */
#define NV_PFB_PRI_MMU_PREFETCH                                     0x001FA3C0 /* RW-4R */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_DISABLE                              0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_DISABLE_FALSE                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_DISABLE_TRUE                  0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_BIG_DISABLE                                1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_PREFETCH_BIG_DISABLE_FALSE                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PREFETCH_BIG_DISABLE_TRUE                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_UNFILLED_DISABLE                           2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_PREFETCH_UNFILLED_DISABLE_FALSE              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PREFETCH_UNFILLED_DISABLE_TRUE               0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_ENGINE                                     5:3 /* RWEVF */
#define NV_PFB_PRI_MMU_PREFETCH_ENGINE_ALL                          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PREFETCH_ENGINE_CE                           0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_ENGINE_VID                          0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_ENGINE_PB                           0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_ATSGPA_DISABLE                             6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_PREFETCH_ATSGPA_DISABLE_FALSE                0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_ATSGPA_DISABLE_TRUE                 0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE                           7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE_FALSE              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE_TRUE               0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE                                 8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE_FALSE                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE_TRUE                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE0                                9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE0_FALSE                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE0_TRUE                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE1                              10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE1_FALSE                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE1_TRUE                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE2                              11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE2_FALSE                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE2_TRUE                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH                       12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_DISABLE          0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_ENABLE           0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE                     15:13 /* RWEVF */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_1              0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_2              0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_4              0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_8              0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_16             0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_32             0x00000005 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_64             0x00000006 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_INCR_ONLY                                20:20 /* RWEVF */
#define NV_PFB_PRI_MMU_PREFETCH_INCR_ONLY_FALSE                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PREFETCH_INCR_ONLY_TRUE                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL                       21:21 /* RWEVF */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL_FALSE            0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL_TRUE             0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_DEBUG_CTRL                                   0x001FA3C4 /* RW-4R */
#define NV_PFB_PRI_MMU_DEBUG_CTRL_WR_KIND                                  7:0 /* RWEVF */
#define NV_PFB_PRI_MMU_DEBUG_CTRL_WR_KIND_INIT                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_DEBUG_CTRL_RD_KIND                                 15:8 /* RWEVF */
#define NV_PFB_PRI_MMU_DEBUG_CTRL_RD_KIND_INIT                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_DEBUG_CTRL_DEBUG                                  16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_DEBUG_CTRL_DEBUG_DISABLED                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_DEBUG_CTRL_DEBUG_ENABLED                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_DEBUG_CTRL_PAGE_SIZE                              18:17 /* RWEVF */
#define NV_PFB_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_4KB                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_64KB                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_128KB                   0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_1MB                     0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_DEBUG_WR                                     0x001FA3C8 /* RW-4R */
#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE                                   1:0 /* RWEVF */
#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_PEER_MEM                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_C                  0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_NC                 0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_DEBUG_WR_VOL                                        2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_DEBUG_WR_VOL_FALSE                           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_DEBUG_WR_VOL_TRUE                            0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_DEBUG_WR_ADDR                                      31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_DEBUG_WR_ADDR_INIT                           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT                      0x0000000c /*       */
#define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_APERTURE                           1:0 /*       */
#define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_APERTURE_VID_MEM            0x00000000 /*       */
#define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_APERTURE_SYS_MEM_C          0x00000002 /*       */
#define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_APERTURE_SYS_MEM_NC         0x00000003 /*       */
#define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_VOL                                2:2 /*       */
#define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_VOL_FALSE                   0x00000000 /*       */
#define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_VOL_TRUE                    0x00000001 /*       */
#define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_ADDR                              31:4 /*       */
#define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_ADDR_ALIGNMENT              0x0000000c /*       */
#define NV_PFB_PRI_MMU_DEBUG_RD                                     0x001FA3CC /* RW-4R */
#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE                                   1:0 /* RWEVF */
#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_PEER_MEM                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_C                  0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_NC                 0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_DEBUG_RD_VOL                                        2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_DEBUG_RD_VOL_FALSE                           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_DEBUG_RD_VOL_TRUE                            0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_DEBUG_RD_ADDR                                      31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_DEBUG_RD_ADDR_INIT                           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT                      0x0000000c /*       */
#define NV_PFB_PRI_MMU_DEBUG_RD_FLA_UPPER_IMB_ADDR                        25:8 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK                                      0x001FA5F4 /* RW-4R */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "dfd_features" /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_dfd_features_wr_secure" /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST                                      0x001FA5F0 /* RW-4R */
#define NV_PFB_PRI_MMU_ADDR_INTEREST__PRIV_LEVEL_MASK                     0x001FA5F4 /*       */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_ENABLE                               0:0        /* RWEVF */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_ENABLE_ENABLED                       0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_ENABLE_DISABLED                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_SEC_REQ                              1:1        /* RWEVF */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_SEC_REQ_ENABLED                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ADDR_INTEREST_SEC_REQ_DISABLED                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UPPER_ADDR_LOW                            0x001FA3F0 /* RW-4R */
#define NV_PFB_PRI_MMU_PM_UPPER_ADDR_LOW_BITS                             23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UPPER_ADDR_LOW_BITS_INIT                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UPPER_ADDR_HIGH                           0x001FA3F4 /* RW-4R */
#define NV_PFB_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS                            23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED                                           0x001FA3D8 /* RW-4R */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED__PRIV_LEVEL_MASK                          0x001FA3DC /*       */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_ENABLE                                           0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_ENABLE_FALSE                              0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_ENABLE_TRUE                               0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_ENABLE_INIT                               0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_SYSWR_ENABLE                                     1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_SYSWR_ENABLE_FALSE                        0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_SYSWR_ENABLE_TRUE                         0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_SYSWR_ENABLE_INIT                         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_FUSE                                             2:2 /* R-XVF */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_FUSE_FALSE                                0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_FUSE_TRUE                                 0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_FORCE_NON_PASID_ATS                              3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_FORCE_NON_PASID_ATS_DISABLE               0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_FORCE_NON_PASID_ATS_ENABLE                0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_FORCE_NON_PASID_ATS_INIT                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_ATSD_OPTIMIZATION                                4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_ATSD_OPTIMIZATION_DISABLE                 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_ATSD_OPTIMIZATION_ENABLE                  0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_ATSD_OPTIMIZATION_INIT                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_CLIENT_CHK                                       7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_CLIENT_CHK_ALL                            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_CLIENT_CHK_ONE                            0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_CLIENT_CHK_INIT                           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_CLIENT_ID                                       15:8 /* RWEVF */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_CLIENT_ID_SEC                             0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_CLIENT_ID_GSP                             0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_CLIENT_ID_PMU                             0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_CLIENT_ID_NVDEC                           0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_MEMORY_LOCKED_CLIENT_ID_INIT                            0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_STATE                                               0x001FA834 /* RW-4R */
#define NV_PFB_PRI_MMU_VPR_STATE__PRIV_LEVEL_MASK                              0x001FA7C0 /*       */
#define NV_PFB_PRI_MMU_VPR_STATE_PROTECTED_MODE                                       0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_STATE_PROTECTED_MODE_FALSE                          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_STATE_PROTECTED_MODE_TRUE                           0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE                                                0x001FA800 /* RW-4R */
#define NV_PFB_PRI_MMU_VPR_MODE__PRIV_LEVEL_MASK           0x001FA7D0 /*       */
#define NV_PFB_PRI_MMU_VPR_MODE_IN_USE                                                0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_MODE_IN_USE_TRUE                                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_IN_USE_FALSE                                   0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_IN_USE_INIT                                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_MODE_FETCH                                                 2:2 /* RWXVF */
#define NV_PFB_PRI_MMU_VPR_MODE_FETCH_FALSE                                    0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_FETCH_INIT                                     0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_FETCH_TRUE                                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_ENCRYPTION                                        5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_ENCRYPTION_FALSE                           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_ENCRYPTION_TRUE                            0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_ENCRYPTION_INIT                            0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_NON_COMPRESSIBLE                                  6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_NON_COMPRESSIBLE_FALSE                     0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_NON_COMPRESSIBLE_TRUE                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_NON_COMPRESSIBLE_INIT                      0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_SWIZID                                           11:8 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_SWIZID_0                                   0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_SWIZID_1                                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_SWIZID_2                                   0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_SWIZID_INIT                                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_SWIZID_ENABLE                                   12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_SWIZID_ENABLE_FALSE                        0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_SWIZID_ENABLE_TRUE                         0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_SWIZID_ENABLE_INIT                         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_MODE_AUTO_FETCH_FUSE                                     26:26 /* R-XVF */
#define NV_PFB_PRI_MMU_VPR_MODE_AUTO_FETCH_FUSE_DISABLED                       0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_VPR_MODE_AUTO_FETCH_FUSE_ENABLED                        0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_VPR_MODE_AUTO_FETCH_FUSE_INIT                           0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_ENABLE_FUSE                                     27:27 /* R-XVF */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_ENABLE_FUSE_DISABLED                       0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_ENABLE_FUSE_ENABLED                        0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_ENABLE_FUSE_INIT                           0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_FAULT_REPORT                                    29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_FAULT_REPORT_DISABLED                      0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_FAULT_REPORT_INIT                          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_FAULT_REPORT_ENABLED                       0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_HWPM                                       30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_HWPM_ENABLED                          0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_HWPM_INIT                             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_HWPM_DISABLED                         0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_MISC                                       28:28 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_MISC_ENABLED                          0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_MISC_INIT                             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_MISC_DISABLED                         0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_ADDR_LO                                                 0x001FA804 /* RW-4R */
#define NV_PFB_PRI_MMU_VPR_ADDR_LO__PRIV_LEVEL_MASK        0x001FA7D0 /*       */
#define NV_PFB_PRI_MMU_VPR_ADDR_LO_VAL                                               31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_ADDR_LO_VAL_INIT                                    0x0fffffff /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_ADDR_LO_ALIGNMENT                                   0x0000000c /*       */
#define NV_PFB_PRI_MMU_VPR_ADDR_HI                                             0x001FA808 /* RW-4R */
#define NV_PFB_PRI_MMU_VPR_ADDR_HI__PRIV_LEVEL_MASK        0x001FA7D0 /*       */
#define NV_PFB_PRI_MMU_VPR_ADDR_HI_VAL                                               31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_ADDR_HI_VAL_INIT                                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_ADDR_HI_ALIGNMENT                                   0x0000000c /*       */
#define NV_PFB_PRI_MMU_VPR_UPPER_ADDR_LO                                           0x001F9D20 /* RW-4R */
#define NV_PFB_PRI_MMU_VPR_UPPER_ADDR_LO__PRIV_LEVEL_MASK        0x001FA7D0 /*       */
#define NV_PFB_PRI_MMU_VPR_UPPER_ADDR_LO_VAL                                         23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_UPPER_ADDR_LO_VAL_INIT                              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_UPPER_ADDR_LO_ALIGNMENT                             0x00000028 /*       */
#define NV_PFB_PRI_MMU_VPR_UPPER_ADDR_HI                                           0x001F9D24 /* RW-4R */
#define NV_PFB_PRI_MMU_VPR_UPPER_ADDR_HI__PRIV_LEVEL_MASK        0x001FA7D0 /*       */
#define NV_PFB_PRI_MMU_VPR_UPPER_ADDR_HI_VAL                                         23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_UPPER_ADDR_HI_VAL_INIT                              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_UPPER_ADDR_HI_ALIGNMENT                             0x00000028 /*       */
#define NV_PFB_PRI_MMU_VPR_CYA_UNTRUSTED                                       0x00000000 /*       */
#define NV_PFB_PRI_MMU_VPR_CYA_GRAPHICS                                        0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_CYA_VPR_AWARE                                       0x00000001 /*       */
#define NV_PFB_PRI_MMU_VPR_CYA_QUARANTINE                                      0x00000002 /*       */
#define NV_PFB_PRI_MMU_VPR_CYA_TRUSTED                                         0x00000003 /*       */
#define NV_PFB_PRI_MMU_VPR_CYA_LO                                              0x001FA80C /* RW-4R */
#define NV_PFB_PRI_MMU_VPR_CYA_LO__PRIV_LEVEL_MASK         0x001FA7D0 /*       */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_DEFAULT                                       5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_DEFAULT_USE_CYA                        0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_DEFAULT_DEFAULT                        0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_DEFAULT_INIT                           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CPU                                           7:6 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CPU_DEFAULT      0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CPU_INIT         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_HOST                                          9:8 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_HOST_DEFAULT     0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_HOST_INIT        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PERF                                        11:10 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PERF_DEFAULT     0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PERF_INIT        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PMU                                         13:12 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PMU_DEFAULT      0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PMU_INIT         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE2                                         15:14 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE2_DEFAULT      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE2_INIT                               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SEC                                         17:16 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SEC_DEFAULT      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SEC_INIT         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_FE                                          19:18 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_FE_DEFAULT       0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_FE_INIT          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PD                                          21:20 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PD_DEFAULT       0x00000001  /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PD_INIT          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SCC                                         23:22 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SCC_DEFAULT      0x00000001  /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SCC_INIT         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SKED                                        25:24 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SKED_DEFAULT     0x00000001  /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SKED_INIT        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_L1                                          27:26 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_L1_DEFAULT       0x00000001  /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_L1_INIT          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_TEX                                         29:28 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_TEX_DEFAULT      0x00000001  /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_TEX_INIT         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PE                                          31:30 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PE_DEFAULT       0x00000001  /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PE_INIT          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI                                              0x001FA810 /* RW-4R */
#define NV_PFB_PRI_MMU_VPR_CYA_HI__PRIV_LEVEL_MASK         0x001FA7D0 /*       */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_RASTER                                        5:4 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_RASTER_DEFAULT   0x00000001  /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_RASTER_INIT      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GCC                                           7:6 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GCC_DEFAULT      0x00000001  /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GCC_INIT         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GPCCS                                         9:8 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GPCCS_DEFAULT    0x00000001  /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GPCCS_INIT       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP                                        11:10 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_DEFAULT     0x00000001  /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_INIT        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_READ                                   12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_READ_DEFAULT                      0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_READ_INIT                         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_WRITE                                  13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_WRITE_DEFAULT                     0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_WRITE_INIT                        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_DNISO                                       15:14 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_DNISO_DEFAULT    0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_DNISO_INIT       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC                                       17:16 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC_DEFAULT    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC_INIT       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC0                                      17:16 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC0_DEFAULT   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC0_INIT      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC2                                      17:16 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC2_DEFAULT   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC2_INIT      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSENC                                       17:16 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSENC_DEFAULT    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSENC_INIT       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVDEC                                       19:18 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVDEC_DEFAULT    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVDEC_INIT       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSPDEC                                      19:18 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSPDEC_DEFAULT   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSPDEC_INIT      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GSP                                         21:20 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GSP_DEFAULT      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GSP_INIT         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC1                                      23:22 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC1_DEFAULT   0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC1_INIT      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSVLD                                       23:22 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSVLD_DEFAULT    0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSVLD_INIT       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_OFA                                     25:24 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_OFA_DEFAULT      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_OFA_INIT         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_FSP                                         27:26 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_FSP_DEFAULT      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_FSP_INIT         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVJPG                                       29:28 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVJPG_DEFAULT    0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVJPG_INIT       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GSPLITE                                       31:30 /* RWEVF */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GSPLITE_DEFAULT    0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GSPLITE_INIT       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE0              15:14
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE0_DEFAULT      0x00000001
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE0_INIT         0x00000000
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE1              15:14
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE1_DEFAULT      0x00000001
#define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE1_INIT         0x00000000
#define NV_PFB_PRI_MMU_WPR_MODE                                                0x001FA3D4 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR_MODE__PRIV_LEVEL_MASK           0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR_MODE_WPR_NON_COMPRESSIBLE                                  9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_MODE_WPR_NON_COMPRESSIBLE_FALSE                     0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_MODE_WPR_NON_COMPRESSIBLE_TRUE                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_MODE_WPR_NON_COMPRESSIBLE_INIT                      0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_MODE_SECURE_LOCK                                         12:12 /* R-XVF */
#define NV_PFB_PRI_MMU_WPR_MODE_SECURE_LOCK_FALSE                              0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_WPR_MODE_SECURE_LOCK_TRUE                               0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_WPR_MODE_WPR_WITH_SECURE_LOCK                                13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_MODE_WPR_WITH_SECURE_LOCK_FALSE                     0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_MODE_WPR_WITH_SECURE_LOCK_INIT                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_MODE_WPR_WITH_SECURE_LOCK_TRUE                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_MODE_SEC_FAULT_FUSE                                      14:14 /* R-XVF */
#define NV_PFB_PRI_MMU_WPR_MODE_SEC_FAULT_FUSE_FALSE                           0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_WPR_MODE_SEC_FAULT_FUSE_TRUE                            0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_WPR_MODE_FORCE_SPA_EQUAL_GPA                                 20:20 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_MODE_FORCE_SPA_EQUAL_GPA_FALSE                      0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_MODE_FORCE_SPA_EQUAL_GPA_INIT                       0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_MODE_FORCE_SPA_EQUAL_GPA_TRUE                       0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_MODE_WPR_ACCESS_SPA_EQUAL_GPA                            21:21 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_MODE_WPR_ACCESS_SPA_EQUAL_GPA_FALSE                 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_MODE_WPR_ACCESS_SPA_EQUAL_GPA_INIT                  0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_MODE_WPR_ACCESS_SPA_EQUAL_GPA_TRUE                  0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_MODE_WPR_OK                                              30:30 /* R-XVF */
#define NV_PFB_PRI_MMU_WPR_MODE_WPR_ENABLE_FUSE                                     31:31 /* R-XVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ                                          0x001FA814 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ__PRIV_LEVEL_MASK     0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_ALL                                            11:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_ALL_DEFAULT                              0x000000ff /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR(i)                  (((i)-1)*4+7):(((i)-1)*4+4) /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR__SIZE_1                                       3 /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR_SECURE(i,j) (((i)-1)*4+(j)+4):(((i)-1)*4+(j)+4) /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR_SECURE__SIZE_1                                3 /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR_SECURE__SIZE_2                                4 /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1                                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_DEFAULT                             0x0000000F /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE0                                    4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE0_DEFAULT                              1 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE0_NO                                   0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE0_YES                                  1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE1                                    5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE1_DEFAULT                              1 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE1_NO                                   0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE1_YES                                  1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE2                                    6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE2_DEFAULT                              1 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE2_NO                                   0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE2_YES                                  1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE3                                    7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE3_DEFAULT                              1 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE3_NO                                   0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE3_YES                                  1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2                                           11:8 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_DEFAULT                             0x0000000F /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE0                                    8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE0_DEFAULT                              1 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE0_NO                                   0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE0_YES                                  1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE1                                    9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE1_DEFAULT                              1 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE1_NO                                   0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE1_YES                                  1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE2                                  10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE2_DEFAULT                              1 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE2_NO                                   0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE2_YES                                  1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE3                                  11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE3_DEFAULT                              1 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE3_NO                                   0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE3_YES                                  1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH                                     31:28 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH_DEFAULT                                 0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH_BIT(i)                  ((i)+28):((i)+28) /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH_BIT__SIZE_1                             4 /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH0                                    28:28 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH0_DEFAULT                                0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH0_NO                                     0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH0_YES                                    1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH1                                    29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH1_DEFAULT                                0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH1_NO                                     0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH1_YES                                    1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH2                                    30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH2_DEFAULT                                0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH2_NO                                     0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH2_YES                                    1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH3                                    31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH3_DEFAULT                                0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH3_NO                                     0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH3_YES                                    1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE                                         0x001FA818 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE__PRIV_LEVEL_MASK    0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_ALL                                           11:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_ALL_DEFAULT                             0x000000cc /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR(i)            (((i)-1)*4+7):(((i)-1)*4+4)      /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR__SIZE_1                                      3 /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR_SECURE(i,j) (((i)-1)*4+(j)+4):(((i)-1)*4+(j)+4) /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR_SECURE__SIZE_1                               3 /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR_SECURE__SIZE_2                               4 /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1                                           7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_DEFAULT                            0x0000000c /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE0                                   4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE0_DEFAULT                             0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE0_NO                                  0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE0_YES                                 1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE1                                   5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE1_DEFAULT                             0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE1_NO                                  0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE1_YES                                 1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE2                                   6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE2_DEFAULT                             1 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE2_NO                                  0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE2_YES                                 1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE3                                   7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE3_DEFAULT                             1 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE3_NO                                  0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE3_YES                                 1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2                                          11:8 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_DEFAULT                            0x0000000c /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE0                                   8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE0_DEFAULT                             0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE0_NO                                  0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE0_YES                                 1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE1                                   9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE1_DEFAULT                             0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE1_NO                                  0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE1_YES                                 1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE2                                 10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE2_DEFAULT                             1 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE2_NO                                  0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE2_YES                                 1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE3                                 11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE3_DEFAULT                             1 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE3_NO                                  0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE3_YES                                 1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH                                    31:28 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH_DEFAULT                                0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH_BIT(i)                 ((i)+28):((i)+28) /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH_BIT__SIZE_1                            4 /*       */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH0                                   28:28 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH0_DEFAULT                               0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH0_NO                                    0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH0_YES                                   1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH1                                   29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH1_DEFAULT                               0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH1_NO                                    0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH1_YES                                   1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH2                                   30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH2_DEFAULT                               0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH2_NO                                    0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH2_YES                                   1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH3                                   31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH3_DEFAULT                               0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH3_NO                                    0 /* RW--V */
#define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH3_YES                                   1 /* RW--V */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO                                            0x001FA81C /* RW-4R */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO__PRIV_LEVEL_MASK       0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO_VAL                                              31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO_VAL_INIT                                   0x0fffffff /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_ADDR_LO_ALIGNMENT                                  0x0000000c /*       */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI                                            0x001FA820 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI__PRIV_LEVEL_MASK       0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI_VAL                                              31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI_VAL_INIT                                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_ADDR_HI_ALIGNMENT                                  0x0000000c /*       */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO                                            0x001FA824 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO__PRIV_LEVEL_MASK       0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO_VAL                                              31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO_VAL_INIT                                   0x0fffffff /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_ADDR_LO_ALIGNMENT                                  0x0000000c /*       */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI                                            0x001FA828 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI__PRIV_LEVEL_MASK       0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL                                              31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL_INIT                                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT                                  0x0000000c /*       */
#define NV_PFB_PRI_MMU_WPR1_UPPER_ADDR_LO                                          0x001F9D28 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR1_UPPER_ADDR_LO__PRIV_LEVEL_MASK 0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR1_UPPER_ADDR_LO_VAL                                        23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_UPPER_ADDR_LO_VAL_INIT                             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_UPPER_ADDR_LO_ALIGNMENT                            0x00000028 /*       */
#define NV_PFB_PRI_MMU_WPR1_UPPER_ADDR_HI                                          0x001F9D2C /* RW-4R */
#define NV_PFB_PRI_MMU_WPR1_UPPER_ADDR_HI__PRIV_LEVEL_MASK 0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR1_UPPER_ADDR_HI_VAL                                        23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_UPPER_ADDR_HI_VAL_INIT                             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_UPPER_ADDR_HI_ALIGNMENT                            0x00000028 /*       */
#define NV_PFB_PRI_MMU_WPR2_UPPER_ADDR_LO                                          0x001F9D30 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR2_UPPER_ADDR_LO__PRIV_LEVEL_MASK 0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR2_UPPER_ADDR_LO_VAL                                        23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_UPPER_ADDR_LO_VAL_INIT                             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_UPPER_ADDR_LO_ALIGNMENT                            0x00000028 /*       */
#define NV_PFB_PRI_MMU_WPR2_UPPER_ADDR_HI                                          0x001F9D34 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR2_UPPER_ADDR_HI__PRIV_LEVEL_MASK 0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR2_UPPER_ADDR_HI_VAL                                        23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_UPPER_ADDR_HI_VAL_INIT                             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_UPPER_ADDR_HI_ALIGNMENT                            0x00000028 /*       */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A                                      0x001FA940 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A__PRIV_LEVEL_MASK   0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NISO                                        0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NISO_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_ISO                                         1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_ISO_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_DNISO                                       2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_DNISO_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_DWBIF                                       3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_DWBIF_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_GSP                                         4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_GSP_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_MMU                                         5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_MMU_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NVDEC                                       6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NVDEC_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NVENC                                       7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NVENC_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NVJPG                                       8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NVJPG_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_OFA                                         9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_OFA_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_PMU                                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_PMU_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_SEC                                       11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_SEC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_XV                                        12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_XV_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_P2P                                       13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_P2P_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_HOST_CPU                                  14:14 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_HOST_CPU_INIT                                 0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_FBFALCON                                  15:15 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_FBFALCON_INIT                                 0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_FSP                                       16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_FSP_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_GSPLITE                                   17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_GSPLITE_INIT                                  0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B                                      0x001FA944 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B__PRIV_LEVEL_MASK  0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PERF                                        0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PERF_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_MFC                                         1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_MFC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_CE                                          2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_CE_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_FE                                          3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_FE_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_FECS                                        4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_FECS_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_GCC                                         5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_GCC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_GPCCS                                       6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_GPCCS_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PD                                          7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PD_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PE                                          8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PE_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PROP                                        9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PROP_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_RAST                                      10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_RAST_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_RASTERTWOD                                11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_RASTERTWOD_INIT                               0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_SCC                                       12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_SCC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_SKED                                      13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_SKED_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_TEX                                       14:14 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_TEX_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_TPCCS                                     15:15 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_TPCCS_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_HOST                                      16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_HOST_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_ESC                                       17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_ESC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A                                      0x001FA948 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A__PRIV_LEVEL_MASK   0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NISO                                        0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NISO_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_ISO                                         1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_ISO_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_DNISO                                       2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_DNISO_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_DWBIF                                       3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_DWBIF_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_GSP                                         4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_GSP_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_MMU                                         5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_MMU_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NVDEC                                       6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NVDEC_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NVENC                                       7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NVENC_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NVJPG                                       8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NVJPG_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_OFA                                         9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_OFA_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_PMU                                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_PMU_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_SEC                                       11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_SEC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_XV                                        12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_XV_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_P2P                                       13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_P2P_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_HOST_CPU                                  14:14 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_HOST_CPU_INIT                                 0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_FBFALCON                                  15:15 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_FBFALCON_INIT                                 0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_FSP                                       16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_FSP_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_GSPLITE                                   17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_GSPLITE_INIT                                  0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B                                      0x001FA94C /* RW-4R */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B__PRIV_LEVEL_MASK  0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PERF                                        0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PERF_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_MFC                                         1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_MFC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_CE                                          2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_CE_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_FE                                          3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_FE_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_FECS                                        4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_FECS_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_GCC                                         5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_GCC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_GPCCS                                       6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_GPCCS_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PD                                          7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PD_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PE                                          8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PE_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PROP                                        9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PROP_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_RAST                                      10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_RAST_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_RASTERTWOD                                11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_RASTERTWOD_INIT                               0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_SCC                                       12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_SCC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_SKED                                      13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_SKED_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_TEX                                       14:14 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_TEX_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_TPCCS                                     15:15 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_TPCCS_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_HOST                                      16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_HOST_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_ESC                                       17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_ESC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A                                      0x001FA7B0 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A__PRIV_LEVEL_MASK   0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NISO                                        0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NISO_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_ISO                                         1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_ISO_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_DNISO                                       2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_DNISO_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_DWBIF                                       3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_DWBIF_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_GSP                                         4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_GSP_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_MMU                                         5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_MMU_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NVDEC                                       6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NVDEC_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NVENC                                       7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NVENC_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NVJPG                                       8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NVJPG_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_OFA                                         9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_OFA_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_PMU                                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_PMU_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_SEC                                       11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_SEC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_XV                                        12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_XV_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_P2P                                       13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_P2P_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_HOST_CPU                                  14:14 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_HOST_CPU_INIT                                 0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_FBFALCON                                  15:15 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_FBFALCON_INIT                                 0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_FSP                                       16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_FSP_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_GSPLITE                                   17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_GSPLITE_INIT                                  0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B                                      0x001FA7B4 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B__PRIV_LEVEL_MASK  0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PERF                                        0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PERF_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_MFC                                         1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_MFC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_CE                                          2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_CE_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_FE                                          3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_FE_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_FECS                                        4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_FECS_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_GCC                                         5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_GCC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_GPCCS                                       6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_GPCCS_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PD                                          7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PD_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PE                                          8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PE_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PROP                                        9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PROP_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_RAST                                      10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_RAST_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_RASTERTWOD                                11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_RASTERTWOD_INIT                               0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_SCC                                       12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_SCC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_SKED                                      13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_SKED_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_TEX                                       14:14 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_TEX_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_TPCCS                                     15:15 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_TPCCS_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_HOST                                      16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_HOST_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_ESC                                       17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_ESC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A                                      0x001FA7B8 /* RW-4R */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A__PRIV_LEVEL_MASK   0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NISO                                        0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NISO_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_ISO                                         1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_ISO_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_DNISO                                       2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_DNISO_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_DWBIF                                       3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_DWBIF_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_GSP                                         4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_GSP_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_MMU                                         5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_MMU_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NVDEC                                       6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NVDEC_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NVENC                                       7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NVENC_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NVJPG                                       8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NVJPG_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_OFA                                         9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_OFA_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_PMU                                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_PMU_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_SEC                                       11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_SEC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_XV                                        12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_XV_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_P2P                                       13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_P2P_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_HOST_CPU                                  14:14 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_HOST_CPU_INIT                                 0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_FBFALCON                                  15:15 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_FBFALCON_INIT                                 0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_FSP                                       16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_FSP_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_GSPLITE                                   17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_GSPLITE_INIT                                  0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B                                      0x001FA7BC /* RW-4R */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B__PRIV_LEVEL_MASK  0x001FA7CC /*       */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PERF                                        0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PERF_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_MFC                                         1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_MFC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_CE                                          2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_CE_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_FE                                          3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_FE_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_FECS                                        4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_FECS_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_GCC                                         5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_GCC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_GPCCS                                       6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_GPCCS_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PD                                          7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PD_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PE                                          8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PE_INIT                                       0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PROP                                        9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PROP_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_RAST                                      10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_RAST_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_RASTERTWOD                                11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_RASTERTWOD_INIT                               0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_SCC                                       12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_SCC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_SKED                                      13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_SKED_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_TEX                                       14:14 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_TEX_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_TPCCS                                     15:15 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_TPCCS_INIT                                    0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_HOST                                      16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_HOST_INIT                                     0 /* RWE-V */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_ESC                                       17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_ESC_INIT                                      0 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCK_ADDR_LO                                                0x001FA82C /* RW-4R */
#define NV_PFB_PRI_MMU_LOCK_ADDR_LO__PRIV_LEVEL_MASK       0x001FA7C8 /*       */
#define NV_PFB_PRI_MMU_LOCK_ADDR_LO_VAL                                              31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_ADDR_LO_VAL_INIT                                   0x0fffffff /* RWE-V */
#define NV_PFB_PRI_MMU_LOCK_ADDR_LO_ALIGNMENT                                  0x0000000c /*       */
#define NV_PFB_PRI_MMU_LOCK_ADDR_HI                                                0x001FA830 /* RW-4R */
#define NV_PFB_PRI_MMU_LOCK_ADDR_HI__PRIV_LEVEL_MASK       0x001FA7C8 /*       */
#define NV_PFB_PRI_MMU_LOCK_ADDR_HI_VAL                                              31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_ADDR_HI_VAL_INIT                                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCK_ADDR_HI_ALIGNMENT                                  0x0000000c /*       */
#define NV_PFB_PRI_MMU_LOCK_UPPER_ADDR_LO                                          0x001F9D58 /* RW-4R */
#define NV_PFB_PRI_MMU_LOCK_UPPER_ADDR_LO__PRIV_LEVEL_MASK       0x001FA7C8 /*       */
#define NV_PFB_PRI_MMU_LOCK_UPPER_ADDR_LO_VAL                                        23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_UPPER_ADDR_LO_VAL_INIT                             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCK_UPPER_ADDR_LO_ALIGNMENT                            0x00000028 /*       */
#define NV_PFB_PRI_MMU_LOCK_UPPER_ADDR_HI                                          0x001F9D5C /* RW-4R */
#define NV_PFB_PRI_MMU_LOCK_UPPER_ADDR_HI__PRIV_LEVEL_MASK       0x001FA7C8 /*       */
#define NV_PFB_PRI_MMU_LOCK_UPPER_ADDR_HI_VAL                                        23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCK_UPPER_ADDR_HI_VAL_INIT                             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCK_UPPER_ADDR_HI_ALIGNMENT                            0x00000028 /*       */
#define NV_PFB_PRI_MMU_VPR_WPR_VAL                                                   31:4 /*       */
#define NV_PFB_PRI_MMU_VPR_WPR_UPPER_VAL                                             23:0 /*       */
#define NV_PFB_PRI_MMU_WPR_ADDR_LO(i)                           (((i)-1)*(0x001FA824-0x001FA81C)+0x001FA81C) /*       */
#define NV_PFB_PRI_MMU_WPR_ADDR_LO__SIZE_1                          3 /*       */
#define NV_PFB_PRI_MMU_WPR_ADDR_HI(i)                           (((i)-1)*(0x001FA828-0x001FA820)+0x001FA820) /*       */
#define NV_PFB_PRI_MMU_WPR_ADDR_HI__SIZE_1                          3 /*       */
#define NV_PFB_PRI_MMU_WPR_UPPER_ADDR_LO(i)                     (((i)-1)*(0x001F9D30-0x001F9D28)+0x001F9D28) /*       */
#define NV_PFB_PRI_MMU_WPR_UPPER_ADDR_LO__SIZE_1                    3 /*       */
#define NV_PFB_PRI_MMU_WPR_UPPER_ADDR_HI(i)                     (((i)-1)*(0x001F9D34-0x001F9D2C)+0x001F9D2C) /*       */
#define NV_PFB_PRI_MMU_WPR_UPPER_ADDR_HI__SIZE_1                    3 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE                           0x001FA3E0 /* RW-4R */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE__PRIV_LEVEL_MASK          0x001FA7C4 /*       */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_SCALE                      3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_SCALE_INIT          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_MAG                       27:4 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_MAG_INIT            0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_ECC_MODE                       30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_ECC_MODE_DISABLED         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_ECC_MODE_ENABLED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK                                      0x001FA5FC /* RW-4R */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_PHYS_SECURE                                  0x001FA3E4 /* RW-4R */
#define NV_PFB_PRI_MMU_PHYS_SECURE__PRIV_LEVEL_MASK                 0x001FA5FC /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_FECS                                    3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_FECS_INIT                        0x0000000F /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PMU                                     7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PMU_INIT                         0x0000000F /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_SEC                                    11:8 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_SEC_INIT                         0x0000000F /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_DFALCON                               15:12 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_DFALCON_INIT                     0x0000000F /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_GSP                                   15:12 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_GSP_INIT                         0x0000000F /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_AFALCON                               19:16 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_AFALCON_INIT                     0x0000000F /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_NVDEC                                 23:20 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_NVDEC_INIT                       0x0000000F /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_NVENC                                 27:24 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_NVENC_INIT                       0x0000000F /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_MSPPP                                 31:28 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_MSPPP_INIT                       0x0000000F /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_FBFALCON                              31:28 /* RWEVF */
#define NV_PFB_PRI_MMU_PHYS_SECURE_FBFALCON_INIT                    0x0000000F /* RWE-V */
#define NV_PFB_PRI_MMU_PHYS_SECURE_FECS_SECURE(i)              ((i)+0):((i)+0) /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_FECS_SECURE__SIZE_1                       4 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PMU_SECURE(i)               ((i)+4):((i)+4) /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_PMU_SECURE__SIZE_1                        4 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_SEC_SECURE(i)               ((i)+8):((i)+8) /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_SEC_SECURE__SIZE_1                        4 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_DFALCON_SECURE(i)         ((i)+12):((i)+12) /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_DFALCON_SECURE__SIZE_1                    4 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_GSP_SECURE(i)             ((i)+12):((i)+12) /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_GSP_SECURE__SIZE_1                        4 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_AFALCON_SECURE(i)         ((i)+16):((i)+16) /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_AFALCON_SECURE__SIZE_1                    4 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_NVDEC_SECURE(i)           ((i)+20):((i)+20) /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_NVDEC_SECURE__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_NVENC_SECURE(i)           ((i)+24):((i)+24) /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_NVENC_SECURE__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_MSPPP_SECURE(i)           ((i)+28):((i)+28) /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_MSPPP_SECURE__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_FBFALCON_SECURE(i)        ((i)+28):((i)+28) /*       */
#define NV_PFB_PRI_MMU_PHYS_SECURE_FBFALCON_SECURE__SIZE_1                   4 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL                                                                                0x001FA500 /* RW-4R */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL__PRIV_LEVEL_MASK                      0x001FAA4C /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_TGT_MASK                                                                             15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_TGT_MASK_INIT                                                                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_TGT_ADDR                                                                            31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_TGT_ADDR_INIT                                                                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER(i)                                                                      (0x001FA504+(i)*4) /* RW-4A */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER__SIZE_1                                                                                  8 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER__PRIV_LEVEL_MASK                        0x001FAA50 /*       */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_TGT_MASK                                                                              15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_TGT_MASK_INIT                                                                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_TGT_ADDR                                                                             31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_TGT_ADDR_INIT                                                                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_GRANULARITY  37 /*       */
#define NV_PFB_PRI_MMU_NON_REPLAY_FAULT_BUFFER               0
#define NV_PFB_PRI_MMU_REPLAY_FAULT_BUFFER                   1
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO(i)                                         (0x001FA524+(i)*20) /* RW-4A */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO__SIZE_1                              2 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO__PRIV_LEVEL_MASK          0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR_MODE                                                  0:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR_MODE_VIRTUAL                                   0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR_MODE_PHYSICAL                                  0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE                                              2:1 /* RWXVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_LOCAL                                 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_SYS_COH                               0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_SYS_NCOH                              0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_VOL                                                   3:3 /* RWXVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR                                                     31:12 /* RWXVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI(i)                                         (0x001FA528+(i)*20) /* RW-4A */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI__SIZE_1                              2 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI__PRIV_LEVEL_MASK          0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI_ADDR                                                      31:0 /* RWXVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET(i)                                      (0x001FA52C+(i)*20) /* RW-4A */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET__SIZE_1                           2 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET__PRIV_LEVEL_MASK       0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_PTR                                                    19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_PTR_RESET                                        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED                                      30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_NO                              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_YES                             0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_CLEAR                           0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW                                              31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_NO                                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_YES                                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_CLEAR                                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT(i)                         (0x001FA530+(i)*20) /* R--4A */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT__SIZE_1                    2 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT__PRIV_LEVEL_MASK     0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_PTR                               19:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_PTR_RESET                   0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED                 30:30 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_NO         0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_YES        0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW                         31:31 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_NO                 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES                0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE(i)                    (0x001FA534+(i)*20) /* RW-4A */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE__SIZE_1                         2 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE__PRIV_LEVEL_MASK    0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL                          19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL_RESET              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR               29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT                 30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES        0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE                      31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE            0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO                                      0x001FA54C /* R--4R */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO__PRIV_LEVEL_MASK     0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE                               1:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_LOCAL                  0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_PEER                   0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_SYS_COH                0x00000002 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_SYS_NCOH               0x00000003 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_ADDR                                      31:12 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_ADDR_RESET                           0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_ADDR_HI                                      0x001FA550 /* R--4R */
#define NV_PFB_PRI_MMU_FAULT_ADDR_HI__PRIV_LEVEL_MASK   0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_ADDR_HI_ADDR                                       31:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_ADDR_HI_ADDR_RESET                           0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INST_LO                                      0x001FA554 /* R--4R */
#define NV_PFB_PRI_MMU_FAULT_INST_LO__PRIV_LEVEL_MASK   0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_ENGINE_ID                                   8:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_ENGINE_ID_RESET                      0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE                                  11:10 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_VID_MEM                     0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_SYS_MEM_COHERENT            0x00000002 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_SYS_MEM_NONCOHERENT         0x00000003 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_RESET                       0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_ADDR                                      31:12 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_ADDR_RESET                           0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INST_HI                                      0x001FA558 /* R--4R */
#define NV_PFB_PRI_MMU_FAULT_INST_HI__PRIV_LEVEL_MASK   0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_INST_HI_ADDR                                       31:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_HI_ADDR_RESET                           0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO                                         0x001FA55C /* R--4R */
#define NV_PFB_PRI_MMU_FAULT_INFO__PRIV_LEVEL_MASK  0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_INFO_FAULT_TYPE                                     4:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_FAULT_TYPE_RESET                        0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT                               7:7 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_RESET                  0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT                                        14:8 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_RESET                            0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE                                  19:16 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_READ                        0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_WRITE                       0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_ATOMIC                      0x00000002 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PREFETCH                    0x00000003 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_READ                   0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_WRITE                  0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC                 0x00000002 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_STRONG          0x00000002 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_PREFETCH               0x00000003 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_WEAK            0x00000004 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_READ                   0x00000008 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_WRITE                  0x00000009 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_ATOMIC                 0x0000000a /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_PREFETCH               0x0000000b /* R---V */
#define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_RESET                       0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_TYPE                                  20:20 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_TYPE_RESET                       0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_GPC_ID                                       28:24 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_GPC_ID_RESET                            0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_PROTECTED_MODE                               29:29 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_PROTECTED_MODE_RESET                    0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN                          30:30 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN_RESET               0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_VALID                                        31:31 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_VALID_RESET                             0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS                                           0x001FA560 /* RW-4R */
#define NV_PFB_PRI_MMU_FAULT_STATUS__PRIV_LEVEL_MASK   0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS                                0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_RESET                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_CLEAR                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_SET                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT                                1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_RESET                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_CLEAR                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_SET                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS                                2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_RESET                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_CLEAR                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_SET                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT                                3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_RESET                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_CLEAR                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_SET                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS                                 4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_RESET                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_CLEAR                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_SET                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT                                 5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_RESET                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_CLEAR                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_SET                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS                               6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_RESET                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_CLEAR                  0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_SET                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT                               7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_RESET                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_CLEAR                  0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_SET                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE                                       8:8 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_RESET                          0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_SET                            0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE                                   9:9 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_RESET                      0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_SET                        0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR                               10:10 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR_RESET                    0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR_SET                      0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR                           11:11 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR_RESET                0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR_SET                  0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW                            12:12 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW_RESET                 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW_SET                   0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW                        13:13 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW_RESET             0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW_SET               0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED                    14:14 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED_RESET         0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED_SET           0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED                15:15 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED_RESET     0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED_SET       0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VAB_ERROR                                      16:16 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VAB_ERROR_RESET                           0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VAB_ERROR_SET                             0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_TYPE                                      29:28 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_TYPE_REPLAYABLE                      1 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_TYPE_NON_REPLAYABLE                  0 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_TYPE_INIT                            0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY                                           30:30 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_FALSE                                0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_TRUE                                 0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VALID                                          31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_RESET                               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_CLEAR                               0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_SET                                 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK                                      0x001FA5AC /* RW-4R */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "sram_ecc" /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 12     /* RW--V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  15 /* RW--V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_sram_ecc_wr_secure" /*       */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL                                  0x001FA56C /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL__PRIV_LEVEL_MASK   0x001FA5AC /*       */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_CORRECTED_ERR             4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK        0x1 /* RW--T */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT        0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP        0x1 /*       */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR           5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK      0x1 /* RW--T */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP      0x0 /*       */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS                                                         0x001FA570 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB0_SA_DATA                            0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB0_SA_DATA_NOT_PENDING                0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB0_SA_DATA_PENDING                    0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB0_SA_DATA                          1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB0_SA_DATA_NOT_PENDING              0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB0_SA_DATA_PENDING                  0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA                             0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA_NOT_PENDING                 0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA_PENDING                     0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA                           1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA_NOT_PENDING               0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA_PENDING                   0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB1_SA_DATA                            2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB1_SA_DATA_NOT_PENDING                0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB1_SA_DATA_PENDING                    0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB1_SA_DATA                          3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB1_SA_DATA_NOT_PENDING              0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB1_SA_DATA_PENDING                  0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW                 16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING       0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING           0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW                17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING          0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW               18:18 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING     0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING         0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW              19:19 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING    0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING        0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_RESET                                                30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_RESET_CLEAR                                            0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_RESET_TASK                                             0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_RESET_INIT                                             0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CORRECTED_ERR_COUNT                 0x001FA574 /* R--4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CORRECTED_ERR_COUNT_TOTAL                 15:0 /* R-EVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT               0 /* R-E-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE               31:16 /* R-EVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT              0 /* R-E-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT               0x001FA578 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL               15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT             0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE             31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT            0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS                            0x001FA57C /* R--4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS_INDEX                      31:0       /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS_CACHELINE                  15:0       /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS_ERROR_MASK                 27:16      /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS_RAM_ID                     31:28      /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS_RAM_ID_L2TLB0_SA_DATA         0x1      /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS_RAM_ID_L2TLB1_SA_DATA         0x2      /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CONTROL                                  0x001FA344 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CONTROL__PRIV_LEVEL_MASK   0x001FA5AC /*       */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR             4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK        0x1 /* RW--T */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT        0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP        0x1 /*       */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR           5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK      0x1 /* RW--T */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP      0x0 /*       */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS                                                         0x001FA348 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA                             0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA_NOT_PENDING                 0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA_PENDING                     0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA                           1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA_NOT_PENDING               0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA_PENDING                   0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW                 16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING       0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING           0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW                17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING          0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW               18:18 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING     0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING         0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW              19:19 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING    0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING        0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_RESET                                                30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_RESET_CLEAR                                            0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_RESET_TASK                                             0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_STATUS_RESET_INIT                                             0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CORRECTED_ERR_COUNT                 0x001FA34C /* R--4R */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CORRECTED_ERR_COUNT_TOTAL                 15:0 /* R-EVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT               0 /* R-E-V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CORRECTED_ERR_COUNT_UNIQUE               31:16 /* R-EVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT              0 /* R-E-V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_UNCORRECTED_ERR_COUNT               0x001FA350 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_UNCORRECTED_ERR_COUNT_TOTAL               15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT             0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_UNCORRECTED_ERR_COUNT_UNIQUE             31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT            0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_ADDRESS                            0x001FA354 /* R--4R */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_ADDRESS_INDEX                      31:0       /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_ADDRESS_CACHELINE                  15:0       /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_ADDRESS_ERROR_MASK                 27:16      /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_ADDRESS_RAM_ID                     31:28      /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB1_ECC_ADDRESS_RAM_ID_L2TLB_SA_DATA         0x1      /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CONTROL                                  0x001FA358 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CONTROL__PRIV_LEVEL_MASK   0x001FA5AC /*       */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR             4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK        0x1 /* RW--T */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT        0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP        0x1 /*       */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR           5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK      0x1 /* RW--T */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP      0x0 /*       */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS                                                         0x001FA35C /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA                             0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA_NOT_PENDING                 0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA_PENDING                     0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA                           1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA_NOT_PENDING               0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA_PENDING                   0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW                 16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING       0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING           0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW                17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING          0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW               18:18 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING     0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING         0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW              19:19 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING    0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING        0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_RESET                                                30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_RESET_CLEAR                                            0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_RESET_TASK                                             0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_STATUS_RESET_INIT                                             0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CORRECTED_ERR_COUNT                 0x001FA360 /* R--4R */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CORRECTED_ERR_COUNT_TOTAL                 15:0 /* R-EVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT               0 /* R-E-V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CORRECTED_ERR_COUNT_UNIQUE               31:16 /* R-EVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT              0 /* R-E-V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_UNCORRECTED_ERR_COUNT               0x001FA364 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_UNCORRECTED_ERR_COUNT_TOTAL               15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT             0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_UNCORRECTED_ERR_COUNT_UNIQUE             31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT            0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_ADDRESS                            0x001FA368 /* R--4R */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_ADDRESS_INDEX                      31:0       /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_ADDRESS_CACHELINE                  15:0       /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_ADDRESS_ERROR_MASK                 27:16      /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_ADDRESS_RAM_ID                     31:28      /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB2_ECC_ADDRESS_RAM_ID_L2TLB_SA_DATA         0x1      /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CONTROL                                  0x001FA36C /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CONTROL__PRIV_LEVEL_MASK   0x001FA5AC /*       */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR             4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK        0x1 /* RW--T */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT        0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP        0x1 /*       */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR           5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK      0x1 /* RW--T */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP      0x0 /*       */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS                                                         0x001FA370 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA                             0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA_NOT_PENDING                 0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA_PENDING                     0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA                           1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA_NOT_PENDING               0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA_PENDING                   0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW                 16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING       0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING           0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW                17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING          0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW               18:18 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING     0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING         0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW              19:19 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING    0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING        0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_RESET                                                30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_RESET_CLEAR                                            0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_RESET_TASK                                             0x1 /* RW--V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_STATUS_RESET_INIT                                             0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CORRECTED_ERR_COUNT                 0x001FA374 /* R--4R */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CORRECTED_ERR_COUNT_TOTAL                 15:0 /* R-EVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT               0 /* R-E-V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CORRECTED_ERR_COUNT_UNIQUE               31:16 /* R-EVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT              0 /* R-E-V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_UNCORRECTED_ERR_COUNT               0x001FA378 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_UNCORRECTED_ERR_COUNT_TOTAL               15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT             0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_UNCORRECTED_ERR_COUNT_UNIQUE             31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT            0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_ADDRESS                            0x001FA37C /* R--4R */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_ADDRESS_INDEX                      31:0       /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_ADDRESS_CACHELINE                  15:0       /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_ADDRESS_ERROR_MASK                 27:16      /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_ADDRESS_RAM_ID                     31:28      /* R-XVF */
#define NV_PFB_PRI_MMU_L2TLB3_ECC_ADDRESS_RAM_ID_L2TLB_SA_DATA         0x1      /* RW--V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL                                  0x001FA580 /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL__PRIV_LEVEL_MASK   0x001FA5AC /*       */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_CORRECTED_ERR             4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK        0x1 /* RW--T */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT        0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP        0x1 /*       */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR           5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK      0x1 /* RW--T */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP      0x0 /*       */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS                                                      0x001FA584 /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_HUBTLB_SA_DATA                           0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_HUBTLB_SA_DATA_NOT_PENDING               0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_HUBTLB_SA_DATA_PENDING                   0x1 /* RW--V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_HUBTLB_SA_DATA                         1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_HUBTLB_SA_DATA_NOT_PENDING             0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_HUBTLB_SA_DATA_PENDING                 0x1 /* RW--V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW                 16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING       0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING           0x1 /* RW--V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW                17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING          0x1 /* RW--V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW               18:18 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING     0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING         0x1 /* RW--V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW              19:19 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING    0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING        0x1 /* RW--V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_RESET                                                30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_RESET_CLEAR                                            0x1 /* RW--V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_RESET_TASK                                             0x1 /* RW--V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_RESET_INIT                                             0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CORRECTED_ERR_COUNT                 0x001FA588 /* R--4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CORRECTED_ERR_COUNT_TOTAL                 15:0 /* R-EVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT               0 /* R-E-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CORRECTED_ERR_COUNT_UNIQUE               31:16 /* R-EVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT              0 /* R-E-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT               0x001FA58C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL               15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT             0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE             31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT            0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_ADDRESS                            0x001FA590 /* R--4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_ADDRESS_INDEX                      31:0       /* R-XVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_ADDRESS_CACHELINE                  11:0       /* R-XVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_ADDRESS_ERROR_MASK                 27:12      /* R-XVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_ADDRESS_RAM_ID                     31:28      /* R-XVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_ADDRESS_RAM_ID_HUBTLB_SA_DATA        0x1      /* RW--V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL                                  0x001FA594 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL__PRIV_LEVEL_MASK   0x001FA5AC /*       */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_CORRECTED_ERR             4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK        0x1 /* RW--T */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT        0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP        0x1 /*       */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_UNCORRECTED_ERR           5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK      0x1 /* RW--T */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP      0x0 /*       */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS                                                      0x001FA598 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_FILLUNIT_PTE_DATA                        0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_FILLUNIT_PTE_DATA_NOT_PENDING            0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_FILLUNIT_PTE_DATA_PENDING                0x1 /* RW--V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_FILLUNIT_PTE_DATA                      1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_FILLUNIT_PTE_DATA_NOT_PENDING          0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_FILLUNIT_PTE_DATA_PENDING              0x1 /* RW--V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_FILLUNIT_PDE0_DATA                       2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_FILLUNIT_PDE0_DATA_NOT_PENDING           0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_FILLUNIT_PDE0_DATA_PENDING               0x1 /* RW--V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_FILLUNIT_PDE0_DATA                     3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_FILLUNIT_PDE0_DATA_NOT_PENDING         0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_FILLUNIT_PDE0_DATA_PENDING             0x1 /* RW--V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW                 16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING       0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING           0x1 /* RW--V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW                17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING          0x1 /* RW--V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW               18:18 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING     0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING         0x1 /* RW--V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW              19:19 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING    0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING        0x1 /* RW--V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_RESET                                                30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_RESET_CLEAR                                            0x1 /* RW--V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_RESET_TASK                                             0x1 /* RW--V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_RESET_INIT                                             0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CORRECTED_ERR_COUNT                 0x001FA59C /* R--4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CORRECTED_ERR_COUNT_TOTAL                 15:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT               0 /* R-E-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CORRECTED_ERR_COUNT_UNIQUE               31:16 /* R-EVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT              0 /* R-E-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT               0x001FA5A0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL               15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT             0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE             31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT            0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS                            0x001FA5A4 /* R--4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS_INDEX                      31:0       /* R-XVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS_CACHELINE                  11:0       /* R-XVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS_ERROR_MASK                 27:12      /* R-XVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS_RAM_ID                     31:28      /* R-XVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS_RAM_ID_FILLUNIT_PTE_DATA     0x1      /* RW--V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS_RAM_ID_FILLUNIT_PDE0_DATA    0x2      /* RW--V */
#define NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR                               0x001FA5A8 /* R--4R */
#define NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR                    0:0 /* R-EVF */
#define NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_NOT_PENDING        0x0 /* R-E-V */
#define NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_PENDING            0x1 /* R---V */
#define NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR                  1:1 /* R-EVF */
#define NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_NOT_PENDING      0x0 /* R-E-V */
#define NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_PENDING          0x1 /* R---V */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL                        0x001FA5B0 /* RW-4R */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL__PRIV_LEVEL_MASK   0x001FA5AC /*       */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_FILL_ERROR_REISSUE                 0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_FILL_ERROR_REISSUE_ENABLE            1 /* RWE-V */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_FILL_ERROR_REISSUE_DISABLE           0 /* RW--V */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_FILL_ERROR_BLACKLIST               1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_FILL_ERROR_BLACKLIST_ENABLE          1 /* RWE-V */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_FILL_ERROR_BLACKLIST_DISABLE         0 /* RW--V */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_HUBTLB_ERROR_REISSUE                 2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_HUBTLB_ERROR_REISSUE_ENABLE            1 /* RWE-V */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_HUBTLB_ERROR_REISSUE_DISABLE           0 /* RW--V */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_HUBTLB_ERROR_BLACKLIST               3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_HUBTLB_ERROR_BLACKLIST_ENABLE          1 /* RWE-V */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_HUBTLB_ERROR_BLACKLIST_DISABLE         0 /* RW--V */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_GPCL2TLB_ERROR_REISSUE                 4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_GPCL2TLB_ERROR_REISSUE_ENABLE            1 /* RWE-V */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_GPCL2TLB_ERROR_REISSUE_DISABLE           0 /* RW--V */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_GPCL2TLB_ERROR_BLACKLIST               5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_GPCL2TLB_ERROR_BLACKLIST_ENABLE          1 /* RWE-V */
#define NV_PFB_PRI_MMU_ERROR_CONTAINMENT_CONTROL_GPCL2TLB_ERROR_BLACKLIST_DISABLE         0 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK                                      0x001FA5B8 /* RW-4R */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  8 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ                                  0x001FA5B4 /* RW-4R */
#define NV_PFB_PRI_MMU_CBC_ADJ__PRIV_LEVEL_MASK                 0x001FA5B8 /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_START_P2                                1:0 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_START_P2_INIT                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_START_NP2                               3:2 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_START_NP2_INIT                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_END_P2                                  5:4 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_END_P2_INIT                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_END_NP2                                 7:6 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_END_NP2_INIT                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_SIZE_P2                                 9:8 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_SIZE_P2_INIT                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_SIZE_NP2                              11:10 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_SIZE_NP2_INIT                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_COMPTAGLINE                           23:12 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_COMPTAGLINE_INIT                 0x00000fff /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_COMPTAGLINE_ALIGNMENT            0x0000000c /*       */
#define NV_PFB_PRI_MMU_CBC_ADJ_BEG_MEM_CHK                           28:28 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_BEG_MEM_CHK_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_BEG_MEM_CHK_DISABLED             0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_BEG_MEM_CHK_ENABLED              0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_END_MEM_CHK                           29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_END_MEM_CHK_INIT                 0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_END_MEM_CHK_DISABLED             0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_END_MEM_CHK_ENABLED              0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_ALWAYS_SAFE                           30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_ADJ_ALWAYS_SAFE_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_ADJ_ALWAYS_SAFE_TRUE                 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_ALWAYS_SAFE_FALSE                0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_ADJ_SAFE                                  31:31 /* C--VF */
#define NV_PFB_PRI_MMU_CBC_ADJ_SAFE_TRUE                        0x00000001 /* C---V */
#define NV_PFB_PRI_MMU_CBC_ADJ_SAFE_FALSE                       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK                                      0x001FA5BC /* RW-4R */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  12 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS                         0x001FA5C0 /* RW-4R */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS__PRIV_LEVEL_MASK        0x001FA9A8 /*       */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_V    6:0 /* R--VF */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_COUNT  6:0 /* R--VF */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE                    13:8 /* R--VF */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_ZERO         0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_TWO          0x00000002 /* R---V */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_FOUR         0x00000004 /* R---V */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_EIGHT        0x00000008 /* R---V */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK                        23:16 /* RWEVF */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER(i)    ((i)+16):((i)+16) /*       */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER__SIZE_1               8 /*       */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_ENABLED      0x00000001 /*       */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_DISABLED     0x00000000 /*       */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_INIT         0x00000000 /*       */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2                     24:24 /* R-EVF */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT           0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_ENABLED        0x00000001 /*       */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_DISABLED       0x00000000 /*       */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM                      25:25 /* RWEVF */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_INIT            0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_ENABLED         0x00000001 /*       */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_DISABLED        0x00000000 /*       */
#define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_SLICES_PER_LTC                            30:28 /* R--VF */
#define NV_PFB_PRI_MMU_CBC_BASE                                 0x001FA5C4 /* RW-4R */
#define NV_PFB_PRI_MMU_CBC_BASE__PRIV_LEVEL_MASK                0x001FA5BC /*       */
#define NV_PFB_PRI_MMU_CBC_BASE_ADDRESS                               25:0 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_BASE_ADDRESS_INIT                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_BASE_ALIGNMENT_SHIFT                         11 /*       */
#define NV_PFB_PRI_MMU_CBC_TOP                                  0x001FA5C8 /* RW-4R */
#define NV_PFB_PRI_MMU_CBC_TOP__PRIV_LEVEL_MASK                 0x001FA5BC /*       */
#define NV_PFB_PRI_MMU_CBC_TOP_SIZE                                   14:0 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_TOP_SIZE_INIT                        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_TOP_ALIGNMENT_SHIFT                          11 /*       */
#define NV_PFB_PRI_MMU_CBC_MAX                                  0x001FA5CC /* RW-4R */
#define NV_PFB_PRI_MMU_CBC_MAX__PRIV_LEVEL_MASK                 0x001FA5BC /*       */
#define NV_PFB_PRI_MMU_CBC_MAX_COMPTAGLINE                            23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_CBC_MAX_COMPTAGLINE_INIT                 0x00ffffff /* RWE-V */
#define NV_PFB_PRI_MMU_CBC_MAX_SAFE                                  31:31 /* C--VF */
#define NV_PFB_PRI_MMU_CBC_MAX_SAFE_TRUE                        0x00000001 /* C---V */
#define NV_PFB_PRI_MMU_CBC_MAX_SAFE_FALSE                       0x00000000 /*       */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL                                         0x001FA5D0 /* RW-4R */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL__PRIV_LEVEL_MASK             0x001FAA48 /*       */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_SRIOV                                          0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_SRIOV_DISABLED                          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_SRIOV_ENABLED                           0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_ATS                                            1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_ATS_DISABLED                            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_ATS_ENABLED                             0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FAULT_SYS_BAR_PT_ON_NB_CPU_ACCESS              2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FAULT_SYS_BAR_PT_ON_NB_CPU_ACCESS_DISABLED  0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FAULT_SYS_BAR_PT_ON_NB_CPU_ACCESS_ENABLED   0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_USE_SMC_VEID_TABLES                            3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_USE_SMC_VEID_TABLES_DISABLE             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_USE_SMC_VEID_TABLES_ENABLE              0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_L2TLB_SELECT_MODE                          4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_L2TLB_SELECT_MODE_INIT                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_L2TLB_SELECT_MODE_THRU_ADDR_HASH        0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_L2TLB_SELECT_MODE_THRU_SMC              0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FORCE_CBC_RAW_MODE                             5:5 /* R-EVF */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FORCE_CBC_RAW_MODE_DISABLE              0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FORCE_CBC_RAW_MODE_ENABLE               0x00000001 /* R-E-V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PAGE_TABLE_V3                                  6:6 /* R-EVF */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PAGE_TABLE_V3_DISABLE                   0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PAGE_TABLE_V3_ENABLE                    0x00000001 /* R-E-V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PRI_FAULT_STALL                                7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PRI_FAULT_STALL_DISABLE                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PRI_FAULT_STALL_ENABLE                  0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_VF_APDB_INVAL                                  8:8 /* C--VF */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_VF_APDB_INVAL_ENABLE                    0x00000000 /* C---V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_VF_APDB_INVAL_DISABLE                   0x00000001 /*       */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_NON_PASID_ATS                                  9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_NON_PASID_ATS_DISABLED                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_NON_PASID_ATS_ENABLED                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PASID_ATS_VOL                                11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PASID_ATS_VOL_FALSE                     0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PASID_ATS_VOL_TRUE                      0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_NON_PASID_ATS_VOL                            12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_NON_PASID_ATS_VOL_FALSE                 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_NON_PASID_ATS_VOL_TRUE                  0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PF_FORCE_DISABLE_COMPRESSION                 13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PF_FORCE_DISABLE_COMPRESSION_FALSE      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PF_FORCE_DISABLE_COMPRESSION_TRUE       0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK(i)                              (0x001FAA58+(i)*4) /* RW-4A */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK__SIZE_1                      6 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED  0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "gin_intr_ctrl" /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 12     /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_gin_intr_ctrl_wr_secure" /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL                    0x000FFFFF /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE                   0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL(i)                                                                   (0x001F8EE4 + (i)*4) /* RW-4A */
#define NV_PFB_PRI_MMU_INTR_CTRL__SIZE_1                                                             6 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL__PRIV_LEVEL_MASK                                 NV_PFB_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_MESSAGE                                                                              31:0 /* RWXUF */
#define NV_PFB_PRI_MMU_INTR_CTRL_MESSAGE_0_INIT                                 3221225600 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_MESSAGE_1_INIT                                      3221225606 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_MESSAGE_2_INIT                                3221225536 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_MESSAGE_3_INIT                            3221225604 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_MESSAGE_4_INIT                          3221225603 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_MESSAGE_5_INIT                      3221225605 /* RW--V */
#define NV_PFB_PRI_MMU_INTR_CTRL_ECC_ERROR_INDEX                                    0x00000000 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_INFO_FAULT_INDEX                                   0x00000001 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_REPLAYABLE_FAULT_INDEX                             0x00000002 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_NON_REPLAYABLE_FAULT_INDEX                         0x00000003 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_REPLAYABLE_FAULT_ERROR_INDEX                       0x00000004 /*       */
#define NV_PFB_PRI_MMU_INTR_CTRL_NON_REPLAYABLE_FAULT_ERROR_INDEX                   0x00000005 /*       */
#define NV_PFB_PRI_MMU_VMMU_CFG0                                                               0x001FA5F8 /* RW-4R */
#define NV_PFB_PRI_MMU_VMMU_CFG0__PRIV_LEVEL_MASK                     0x001FAA48 /*       */
#define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE                                                         2:0 /* RWEVF */
#define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_32MB                                                    0x0 /* RW--V */
#define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_64MB                                                    0x1 /* RW--V */
#define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_128MB                                                   0x2 /* RW--V */
#define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_256MB                                                   0x3 /* RW--V */
#define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_512MB                                                   0x4 /* RW--V */
#define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_1024MB                                                  0x5 /* RW--V */
#define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_INIT                 4 /* RWE-V */
#define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_ALIGN               25 /*       */
#define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID                                                  31:16 /* R-EVF */
#define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID_INIT                      1024 /* R-E-V */
#define NV_PFB_PRI_MMU_SRIOV_VMMU_TABLE(i)                                            (0x001F0000+(i)*4) /* RW-4A */
#define NV_PFB_PRI_MMU_SRIOV_VMMU_TABLE__SIZE_1                            2048 /*       */
#define NV_PFB_PRI_MMU_SRIOV_VMMU_TABLE__PRIV_LEVEL_MASK             0x001FAA48 /*       */
#define NV_PFB_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP                                                      31:0 /* RWEVF */
#define NV_PFB_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP_INIT                                           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID(i)                                               (0x001F4000+(i)*4) /* RW-4A */
#define NV_PFB_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID__SIZE_1                           2048 /*       */
#define NV_PFB_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID__PRIV_LEVEL_MASK         0x001FAA48 /*       */
#define NV_PFB_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID_BITMAP                                                     31:0 /* RWEVF */
#define NV_PFB_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID_BITMAP_INIT                                          0xffffffff /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT(i,j)             (0x001F2000+((i)*128)+((j)*20)) /* RW-4A */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT__SIZE_1                                                          64 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT__SIZE_2                                                           2 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT__PRIV_LEVEL_MASK      0x001FAA70          /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT_ADDR_MODE             0:0      /* R--VF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT_PHYS_APERTURE         2:1  /* RWXVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT_PHYS_VOL              3:3       /* RWXVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT_ADDR                  31:12           /* RWXVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI_VIRT(i,j)             (0x001F2004+((i)*128)+((j)*20)) /* RW-4A */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI_VIRT__SIZE_1                                                          64 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI_VIRT__SIZE_2                                                           2 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI_VIRT__PRIV_LEVEL_MASK      0x001FAA70          /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI_VIRT_ADDR                  31:0 /* RWXVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT(i,j)            (0x001F2008+((i)*128)+((j)*20)) /* RW-4A */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT__SIZE_1                                                         64 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT__SIZE_2                                                          2 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT__PRIV_LEVEL_MASK     0x001FAA70          /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT_PTR              19:0               /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT_PTR_RESET                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT_GETPTR_CORRUPTED 30:30  /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT_GETPTR_CORRUPTED_NO        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT_OVERFLOW         31:31          /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT_OVERFLOW_NO                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT(i,j)            (0x001F200C+((i)*128)+((j)*20)) /* R--4A */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT__SIZE_1                                                         64 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT__SIZE_2                                                          2 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT__PRIV_LEVEL_MASK     0x001FAA70          /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT_PTR              19:0               /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT_PTR_RESET                   0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT_GETPTR_CORRUPTED 30:30  /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT_GETPTR_CORRUPTED_NO         0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT_OVERFLOW         31:31          /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT_OVERFLOW_NO                 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT(i,j)           (0x001F2010+((i)*128)+((j)*20)) /* RW-4A */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT__SIZE_1                                                        64 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT__SIZE_2                                                         2 /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT__PRIV_LEVEL_MASK    0x001FAA70          /*       */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_VAL             19:0              /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_VAL_RESET              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_OVERFLOW_INTR   29:29    /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_OVERFLOW_INTR_DISABLE  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_SET_DEFAULT     30:30      /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_SET_DEFAULT_NO         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_ENABLE          31:31           /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_ENABLE_FALSE           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT(i)                          (0x001F203C+((i)*128)) /* R--4A */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT__SIZE_1                                                            64 /*       */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT__PRIV_LEVEL_MASK                 0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT_PHYS_APERTURE       1:0        /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT_PHYS_APERTURE_LOCAL                  0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT_ADDR                31:12                 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT_ADDR_RESET                           0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_ADDR_HI_VIRT(i)                          (0x001F2040+((i)*128)) /* R--4A */
#define NV_PFB_PRI_MMU_FAULT_ADDR_HI_VIRT__SIZE_1                                                            64 /*       */
#define NV_PFB_PRI_MMU_FAULT_ADDR_HI_VIRT__PRIV_LEVEL_MASK                 0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_ADDR_HI_VIRT_ADDR                31:0                 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_ADDR_HI_VIRT_ADDR_RESET                           0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT(i)                          (0x001F2044+((i)*128)) /* R--4A */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT__SIZE_1                                                            64 /*       */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT__PRIV_LEVEL_MASK         0x001FAA70         /*       */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT_ENGINE_ID           8:0            /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT_ENGINE_ID_RESET                      0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT_APERTURE            11:10             /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT_APERTURE_RESET                       0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT_ADDR                31:12                 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT_ADDR_RESET                           0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INST_HI_VIRT(i)                          (0x001F2048+((i)*128)) /* R--4A */
#define NV_PFB_PRI_MMU_FAULT_INST_HI_VIRT__SIZE_1                                                            64 /*       */
#define NV_PFB_PRI_MMU_FAULT_INST_HI_VIRT__PRIV_LEVEL_MASK                 0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_INST_HI_VIRT_ADDR                31:0                 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INST_HI_VIRT_ADDR_RESET                           0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT(i)       (0x001F204C+((i)*128)) /* R--4A */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT__SIZE_1                                         64 /*       */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT__PRIV_LEVEL_MASK       0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_FAULT_TYPE                                     4:0 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_FAULT_TYPE_RESET                        0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_REPLAYABLE_FAULT                               7:7 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_REPLAYABLE_FAULT_RESET                  0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_CLIENT                                        14:8 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_CLIENT_RESET                            0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_ACCESS_TYPE                                  19:16 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_ACCESS_TYPE_RESET                       0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_CLIENT_TYPE                                  20:20 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_CLIENT_TYPE_RESET                       0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_GPC_ID                                       28:24 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_GPC_ID_RESET                            0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_PROTECTED_MODE                               29:29 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_PROTECTED_MODE_RESET                    0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_REPLAYABLE_FAULT_EN                          30:30 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_REPLAYABLE_FAULT_EN_RESET               0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_VALID                                        31:31 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_VALID_RESET                             0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT(i)         (0x001F2050+((i)*128)) /* RW-4A */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT__SIZE_1                                           64 /*       */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT__PRIV_LEVEL_MASK   0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR1_PHYS                                0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR1_PHYS_RESET                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR1_VIRT                                1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR1_VIRT_RESET                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR2_PHYS                                2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR2_PHYS_RESET                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR2_VIRT                                3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR2_VIRT_RESET                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_IFB_PHYS                                 4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_IFB_PHYS_RESET                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_IFB_VIRT                                 5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_IFB_VIRT_RESET                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_OTHER_PHYS                               6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_OTHER_PHYS_RESET                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_OTHER_VIRT                               7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_OTHER_VIRT_RESET                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE                                       8:8 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE_RESET                          0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE                                   9:9 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE_RESET                      0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE_ERROR                               10:10 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE_ERROR_RESET                    0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE_ERROR                           11:11 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE_ERROR_RESET                0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE_OVERFLOW                            12:12 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE_OVERFLOW_RESET                 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE_OVERFLOW                        13:13 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE_OVERFLOW_RESET             0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE_GETPTR_CORRUPTED                    14:14 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE_GETPTR_CORRUPTED_RESET         0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE_GETPTR_CORRUPTED                15:15 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE_GETPTR_CORRUPTED_RESET     0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_VAB_ERROR                                      16:16 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_VAB_ERROR_RESET                           0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_BUSY_TYPE                                      29:28 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_BUSY_TYPE_RESET                           0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_BUSY                                           30:30 /* R-EVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_BUSY_FALSE                                0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_VALID                                          31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_VALID_RESET                               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VADDR_VIRT(i)               (0x001F2054+((i)*128)) /* RW-4A */
#define NV_PFB_PRI_MMU_INVALIDATE_VADDR_VIRT__SIZE_1                                                 64 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_VADDR_VIRT__PRIV_LEVEL_MASK  0x001FAA74 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_VADDR_VIRT_BITS                                                  31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VADDR_VIRT_BITS_INIT                                       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_VIRT(i)         (0x001F2058+((i)*128)) /* RW-4A */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_VIRT__SIZE_1                                           64 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_VIRT__PRIV_LEVEL_MASK  0x001FAA74 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_VIRT_BITS                                            19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_VIRT_BITS_INIT                                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT(i)                 (0x001F205C+((i)*128)) /* RW-4A */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT__SIZE_1                                                   64 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT__PRIV_LEVEL_MASK     0x001FAA74 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT_APERTURE                                                 1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT_APERTURE_INIT                                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT_ADDR                                                    31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT_ADDR_INIT                                         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_VIRT(i)           (0x001F2060+((i)*128)) /* RW-4A */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_VIRT__SIZE_1                                             64 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_VIRT__PRIV_LEVEL_MASK 0x001FAA74 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_VIRT_ADDR                                              19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_VIRT_ADDR_INIT                                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_PASID_VIRT(i)               (0x001F2064+((i)*128)) /* RW-4A */
#define NV_PFB_PRI_MMU_INVALIDATE_PASID_VIRT__SIZE_1                                                 64 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PASID_VIRT__PRIV_LEVEL_MASK   0x001FAA74 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_PASID_VIRT_VAL                                                   19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_PASID_VIRT_VAL_INIT                                        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VIRT(i)                (0x001F2068+((i)*128)) /* RW-4A */
#define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VIRT__SIZE_1                                                  64 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VIRT__PRIV_LEVEL_MASK  0x001FAA74 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VIRT_VAL                                                     5:0 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VIRT_VAL_INIT                                         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VIRT_GFID                                                  31:26 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VIRT_GFID_INIT                                        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT(i)                     (0x001F206C+((i)*128)) /* RW-4A */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT__SIZE_1                                                       64 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT__PRIV_LEVEL_MASK       0x001FAA74 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_ALL_VA                                                       0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_ALL_VA_INIT                                           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_ALL_PDB                                                      1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_ALL_PDB_INIT                                          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_HUBTLB_ONLY                                                  2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_HUBTLB_ONLY_INIT                                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_REPLAY                                                       5:3 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_REPLAY_INIT                                           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_SYS_MEMBAR                                                   6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_SYS_MEMBAR_INIT                                       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_ACK                                                          8:7 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_ACK_INIT                                              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CANCEL_CLIENT_ID                                            14:9 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CANCEL_CLIENT_ID_INIT                                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CANCEL_GPC_ID                                              19:15 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CANCEL_GPC_ID_INIT                                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_INVAL_SCOPE                                                16:15 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_INVAL_SCOPE_ALL_TLBS                                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_INVAL_SCOPE_LINK_TLBS                                 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_INVAL_SCOPE_NON_LINK_TLBS                             0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CANCEL_CLIENT_TYPE                                         20:20 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CANCEL_CLIENT_TYPE_INIT                               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_USE_PASID                                                  21:21 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_USE_PASID_INIT                                        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_USE_SIZE                                                   22:22 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_USE_SIZE_INIT                                         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_PROP_FLUSH                                                 23:23 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_PROP_FLUSH_INIT                                       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CACHE_LEVEL                                                26:24 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CACHE_LEVEL_INIT                                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_SKIPPED                                                    30:30 /* C--VF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_SKIPPED_FALSE                                         0x00000000 /* C---V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_SKIPPED_TRUE                                          0x00000001 /*       */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_TRIGGER                                                    31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_TRIGGER_FALSE                                         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_INVALIDATE_VIRT_TRIGGER_TRUE                                          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_VIRT(i)                (0x001F207C+((i)*128)) /* RW-4A */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_VIRT__SIZE_1                              64 /*       */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_VIRT__PRIV_LEVEL_MASK  0x001FAA70 /*       */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_VIRT_PRF_FILTER                          1:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_VIRT_PRF_FILTER_SEND_ALL          0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_VIRT_PRF_FILTER_SEND_NONE         0x00000003 /* RWE-V */
#define NV_PFB_PRI_MMU_PEER_SUPPORT                                                         0x001FA5D4 /* RW-4R */
#define NV_PFB_PRI_MMU_PEER_SUPPORT__PRIV_LEVEL_MASK               0x001FAA48 /*       */
#define NV_PFB_PRI_MMU_PEER_SUPPORT_GFID                                                           7:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PEER_SUPPORT_GFID_INIT                                               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PEER_SUPPORT_MAX_PEER_ID                                                   10:8 /* RWEVF */
#define NV_PFB_PRI_MMU_PEER_SUPPORT_MAX_PEER_ID_INIT                                        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PEER_SUPPORT_FLA                                                          11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_PEER_SUPPORT_FLA_DISABLED                                            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_SUPPORT_FLA_ENABLED                                             0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGA(i)                          (0x001F8F00+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGA__SIZE_1                     4 /*       */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGA__PRIV_LEVEL_MASK            0x001FA7D4 /*       */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGA_ALLOW_READ                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGA_ALLOW_READ_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGA_ADDR_LO                           31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGA_ADDR_LO_INIT                0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGB(i)                          (0x001F8F04+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGB__SIZE_1                     4 /*       */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGB__PRIV_LEVEL_MASK            0x001FA7D4 /*       */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGB_ALLOW_WRITE                        3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGB_ALLOW_WRITE_INIT            0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGB_ADDR_HI                           31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGB_ADDR_HI_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGA(i)                           (0x001F8FC0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGA__PRIV_LEVEL_MASK             0x001FA838 /*       */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGB(i)                           (0x001F8FC4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGB__PRIV_LEVEL_MASK             0x001FA838 /*       */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGA(i)                           (0x001F9000+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGA__SIZE_1                      8 /*       */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGA__PRIV_LEVEL_MASK             0x001FA7D8 /*       */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGB(i)                           (0x001F9004+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGB__SIZE_1                      8 /*       */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGB__PRIV_LEVEL_MASK             0x001FA7D8 /*       */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGA(i)                           (0x001F9040+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGA__SIZE_1                      8 /*       */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGA__PRIV_LEVEL_MASK             0x001FA7DC /*       */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGB(i)                           (0x001F9044+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGB__SIZE_1                      8 /*       */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGB__PRIV_LEVEL_MASK             0x001FA7DC /*       */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGA(i)                           (0x001F9080+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGA__SIZE_1                      8 /*       */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGA__PRIV_LEVEL_MASK             0x001FA7EC /*       */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGB(i)                           (0x001F9084+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGB__SIZE_1                      8 /*       */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGB__PRIV_LEVEL_MASK             0x001FA7EC /*       */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGA(i)                           (0x001F90C0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGA__PRIV_LEVEL_MASK             0x001FA7F0 /*       */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGB(i)                           (0x001F90C4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGB__PRIV_LEVEL_MASK             0x001FA7F0 /*       */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGA(i)                           (0x001F9100+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGA__PRIV_LEVEL_MASK             0x001FA7F4 /*       */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGB(i)                           (0x001F9104+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGB__PRIV_LEVEL_MASK             0x001FA7F4 /*       */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGA(i)                           (0x001F9140+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGA__PRIV_LEVEL_MASK             0x001FA7F8 /*       */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGB(i)                           (0x001F9144+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGB__PRIV_LEVEL_MASK             0x001FA7F8 /*       */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGA(i)                           (0x001F91C0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGA__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGB(i)                           (0x001F91C4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGB__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGA(i)                           (0x001F9200+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGA__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGB(i)                           (0x001F9204+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGB__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGA(i)                           (0x001F9240+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGA__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGB(i)                           (0x001F9244+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGB__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGA(i)                           (0x001F9280+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGA__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGB(i)                           (0x001F9284+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGB__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGA(i)                           (0x001F92A0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGA__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGB(i)                           (0x001F92A4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGB__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGA(i)                           (0x001F91E0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGA__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGB(i)                           (0x001F91E4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGB__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGA(i)                           (0x001F9220+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGA__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGB(i)                           (0x001F9224+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGB__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGA(i)                           (0x001F9260+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGA__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGB(i)                           (0x001F9264+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGB__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGA(i)                           (0x001F92C0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGA__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGB(i)                           (0x001F92C4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGB__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGA(i)                           (0x001F9300+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGA__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGB(i)                           (0x001F9304+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGB__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGA(i)                           (0x001F9340+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGA__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGB(i)                           (0x001F9344+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGB__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGA(i)                           (0x001F9380+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGA__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGB(i)                           (0x001F9384+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGB__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGA(i)                           (0x001F92E0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGA__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGB(i)                           (0x001F92E4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGB__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGA(i)                           (0x001F9320+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGA__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGB(i)                           (0x001F9324+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGB__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGA(i)                           (0x001F9360+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGA__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGB(i)                           (0x001F9364+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGB__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGA(i)                           (0x001F93A0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGA__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGB(i)                           (0x001F93A4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGB__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGA(i)                              (0x001FA8A0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGA__SIZE_1                         4 /*       */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGA__PRIV_LEVEL_MASK                0x001FA8E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGA_ALLOW_READ                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGA_ALLOW_READ_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGA_ADDR_LO                               31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGA_ADDR_LO_INIT                    0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGB(i)                              (0x001FA8A4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGB__SIZE_1                         4 /*       */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGB__PRIV_LEVEL_MASK                0x001FA8E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGB_ALLOW_WRITE                            3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGB_ALLOW_WRITE_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGB_ADDR_HI                               31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGB_ADDR_HI_INIT                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGA(i)                           (0x001F93C0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGA__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGB(i)                           (0x001F93C4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGB__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGA(i)                           (0x001F9400+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGA__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGB(i)                           (0x001F9404+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGB__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGA(i)                           (0x001F9440+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGA__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGB(i)                           (0x001F9444+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGB__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGA(i)                           (0x001F9480+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGA__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGB(i)                           (0x001F9484+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGB__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGA(i)                           (0x001F93E0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGA__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGB(i)                           (0x001F93E4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGB__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGA(i)                           (0x001F9420+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGA__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGB(i)                           (0x001F9424+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGB__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGA(i)                           (0x001F9460+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGA__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGB(i)                           (0x001F9464+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGB__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGA(i)                           (0x001F94A0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGA__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGA__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGA_ALLOW_READ                          3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGA_ALLOW_READ_INIT              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGA_ADDR_LO                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGA_ADDR_LO_INIT                 0x0FFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGB(i)                           (0x001F94A4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGB__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGB__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGB_ALLOW_WRITE                         3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGB_ALLOW_WRITE_INIT             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGB_ADDR_HI                            31:4 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGB_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGC(i)                            (0x001F9840+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGC__SIZE_1                     4 /*       */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGC__PRIV_LEVEL_MASK            0x001FA7D4 /*       */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGD(i)                            (0x001F9844+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGD__SIZE_1                     4 /*       */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGD__PRIV_LEVEL_MASK            0x001FA7D4 /*       */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_OFA0_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGC(i)                             (0x001F9860+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGC__PRIV_LEVEL_MASK             0x001FA838 /*       */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGC_UPPER_ADDR_LO                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGC_UPPER_ADDR_LO_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGD(i)                             (0x001F9864+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGD__PRIV_LEVEL_MASK             0x001FA838 /*       */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGD_UPPER_ADDR_HI                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FSP_CFGD_UPPER_ADDR_HI_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGC(i)                             (0x001F9880+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGC__SIZE_1                      8 /*       */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGC__PRIV_LEVEL_MASK             0x001FA7D8 /*       */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGC_UPPER_ADDR_LO                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGC_UPPER_ADDR_LO_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGD(i)                             (0x001F9884+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGD__SIZE_1                      8 /*       */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGD__PRIV_LEVEL_MASK             0x001FA7D8 /*       */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGD_UPPER_ADDR_HI                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_PMU_CFGD_UPPER_ADDR_HI_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGC(i)                             (0x001F98C0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGC__SIZE_1                      8 /*       */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGC__PRIV_LEVEL_MASK             0x001FA7DC /*       */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGD(i)                             (0x001F98C4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGD__SIZE_1                      8 /*       */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGD__PRIV_LEVEL_MASK             0x001FA7DC /*       */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_SEC_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGC(i)                             (0x001F9900+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGC__SIZE_1                      8 /*       */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGC__PRIV_LEVEL_MASK             0x001FA7EC /*       */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGC_UPPER_ADDR_LO                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGC_UPPER_ADDR_LO_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGD(i)                             (0x001F9904+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGD__SIZE_1                      8 /*       */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGD__PRIV_LEVEL_MASK             0x001FA7EC /*       */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGD_UPPER_ADDR_HI                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_GSP_CFGD_UPPER_ADDR_HI_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGC(i)                             (0x001F9940+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGC__PRIV_LEVEL_MASK             0x001FA7F0 /*       */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGC_UPPER_ADDR_LO                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGC_UPPER_ADDR_LO_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGD(i)                             (0x001F9944+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGD__PRIV_LEVEL_MASK             0x001FA7F0 /*       */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGD_UPPER_ADDR_HI                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FECS_CFGD_UPPER_ADDR_HI_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGC(i)                             (0x001F9960+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGC__PRIV_LEVEL_MASK             0x001FA7F4 /*       */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGC_UPPER_ADDR_LO                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGC_UPPER_ADDR_LO_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGD(i)                             (0x001F9964+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGD__PRIV_LEVEL_MASK             0x001FA7F4 /*       */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGD_UPPER_ADDR_HI                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGD_UPPER_ADDR_HI_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGC(i)                             (0x001F9980+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGC__PRIV_LEVEL_MASK             0x001FA7F8 /*       */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGC_UPPER_ADDR_LO                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGC_UPPER_ADDR_LO_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGD(i)                             (0x001F9984+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGD__PRIV_LEVEL_MASK             0x001FA7F8 /*       */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGD_UPPER_ADDR_HI                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGD_UPPER_ADDR_HI_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGC(i)                             (0x001F99C0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGC__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGC_UPPER_ADDR_LO                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGC_UPPER_ADDR_LO_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGD(i)                             (0x001F99C4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGD__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGD_UPPER_ADDR_HI                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGD_UPPER_ADDR_HI_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGC(i)                             (0x001F99E0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGC__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGC_UPPER_ADDR_LO                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGC_UPPER_ADDR_LO_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGD(i)                             (0x001F99E4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGD__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGD_UPPER_ADDR_HI                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGD_UPPER_ADDR_HI_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGC(i)                             (0x001F9A00+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGC__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGC_UPPER_ADDR_LO                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGC_UPPER_ADDR_LO_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGD(i)                             (0x001F9A04+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGD__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGD_UPPER_ADDR_HI                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGD_UPPER_ADDR_HI_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGC(i)                             (0x001F9A20+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGC__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGC_UPPER_ADDR_LO_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGD(i)                             (0x001F9A24+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGD__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGD_UPPER_ADDR_HI                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGD_UPPER_ADDR_HI_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGC(i)                             (0x001F9A40+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGC__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGC_UPPER_ADDR_LO                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGC_UPPER_ADDR_LO_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGD(i)                             (0x001F9A44+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGD__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGD_UPPER_ADDR_HI                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGD_UPPER_ADDR_HI_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGC(i)                             (0x001F9A60+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGC__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGC_UPPER_ADDR_LO                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGC_UPPER_ADDR_LO_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGD(i)                             (0x001F9A64+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGD__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGD_UPPER_ADDR_HI                            23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC5_CFGD_UPPER_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGC(i)                             (0x001F9A80+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGC__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGC_UPPER_ADDR_LO                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGC_UPPER_ADDR_LO_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGD(i)                             (0x001F9A84+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGD__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGD_UPPER_ADDR_HI                            23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC6_CFGD_UPPER_ADDR_HI_INIT                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGC(i)                             (0x001F9AA0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGC__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGD(i)                             (0x001F9AA4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGD__PRIV_LEVEL_MASK             0x001FA7E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVDEC7_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGC(i)                             (0x001F9AC0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGC__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGD(i)                             (0x001F9AC4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGD__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGC(i)                             (0x001F9AE0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGC__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGD(i)                             (0x001F9AE4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGD__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGC(i)                             (0x001F9B00+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGC__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGD(i)                             (0x001F9B04+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGD__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGC(i)                             (0x001F9B20+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGC__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGD(i)                             (0x001F9B24+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGD__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGC(i)                             (0x001F9B40+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGC__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGD(i)                             (0x001F9B44+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGD__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC4_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGC(i)                             (0x001F9B60+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGC__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGD(i)                             (0x001F9B64+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGD__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC5_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGC(i)                             (0x001F9B80+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGC__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGD(i)                             (0x001F9B84+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGD__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC6_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGC(i)                             (0x001F9BA0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGC__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGD(i)                             (0x001F9BA4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGD__PRIV_LEVEL_MASK             0x001FA7E4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVENC7_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGC(i)                                (0x001F9BC0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGC__SIZE_1                         4 /*       */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGC__PRIV_LEVEL_MASK                0x001FA8E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGC_UPPER_ADDR_LO                             23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGC_UPPER_ADDR_LO_INIT                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGD(i)                                (0x001F9BC4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGD__SIZE_1                         4 /*       */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGD__PRIV_LEVEL_MASK                0x001FA8E0 /*       */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGD_UPPER_ADDR_HI                             23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_ESC_CFGD_UPPER_ADDR_HI_INIT                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGC(i)                             (0x001F9BE0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGC__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGD(i)                             (0x001F9BE4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGD__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGC(i)                             (0x001F9C00+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGC__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGD(i)                             (0x001F9C04+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGD__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGC(i)                             (0x001F9C20+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGC__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGD(i)                             (0x001F9C24+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGD__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGC(i)                             (0x001F9C40+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGC__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGD(i)                             (0x001F9C44+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGD__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGC(i)                             (0x001F9C60+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGC__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGD(i)                             (0x001F9C64+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGD__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG4_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGC(i)                             (0x001F9C80+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGC__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGD(i)                             (0x001F9C84+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGD__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG5_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGC(i)                             (0x001F9CA0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGC__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGC_UPPER_ADDR_LO                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGC_UPPER_ADDR_LO_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGD(i)                             (0x001F9CA4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGD__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG6_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGC(i)                             (0x001F9CE0+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGC__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGC__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGC_UPPER_ADDR_LO                           23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGC_UPPER_ADDR_LO_INIT                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGD(i)                             (0x001F9CE4+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGD__SIZE_1                      4 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGD__PRIV_LEVEL_MASK             0x001FA7E8 /*       */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGD_UPPER_ADDR_HI                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FALCON_NVJPG7_CFGD_UPPER_ADDR_HI_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK                                      0x001FAA54 /* RW-4R */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  15 /* RWE-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED    0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0(i)                           (0x001F94C0+(i)*4) /* RW-4A */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0__SIZE_1     8 /*       */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0__PRIV_LEVEL_MASK                          0x001FAA54 /*       */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_REMOTE_SWIZID                              3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_REMOTE_SWIZID_INIT                           0 /* RWE-V */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_LOCAL_SWIZID                               9:8 /* RWEVF */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_LOCAL_SWIZID_INIT                            0 /* RWE-V */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_LOCAL_SWIZID_ALL                             0 /* RW--V */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_LOCAL_SWIZID_ONE                             1 /* RW--V */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_LOCAL_SWIZID_GUEST                           2 /* RW--V */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_MMU_L2TLB_SELECT                         14:12 /* RWEVF */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_MMU_L2TLB_SELECT_INIT                      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_MMU_L2TLB_MODE                           15:15 /* RWEVF */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_MMU_L2TLB_MODE_INIT                        0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_MMU_L2TLB_MODE_OWN                         0x0 /* RW--V */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_MMU_L2TLB_MODE_USE_SELECT                  0x1 /* RW--V */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_MMU_ENG_VEID_OFFSET                      21:16 /* C--VF */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_MMU_ENG_VEID_OFFSET_INIT                     0 /* C---V */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_VEID_MAX                                 29:24 /* C--VF */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_VEID_MAX_INIT                                0 /* C---V */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_1(i)                          (0x001F94E0+(i)*4) /* RW-4A */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_1__SIZE_1     8 /*       */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_1__PRIV_LEVEL_MASK             0x001FAA54 /*       */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_1_GPC_MASK                                  15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_1_GPC_MASK_INIT                                0 /* RWE-V */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_1_GPC_MASK_HW          8:0 /* RWEVF */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_1_GPC_MASK_HW_INIT                             0 /* RWE-V */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_1_VEID_MASK                                31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_SMC_ENG_CFG_1_VEID_MASK_INIT                               0 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG(i)                   (0x001F9500+(i)*4) /* RW-4A */
#define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG__SIZE_1       64 /*       */
#define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG__PRIV_LEVEL_MASK                    0x001FAA54 /*       */
#define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_GUEST_VEID_OFFSET                   5:0 /* C--VF */
#define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_GUEST_VEID_OFFSET_INIT              0x0 /* C---V */
#define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_BAR_REMOTE_SWIZID                  11:8 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_BAR_REMOTE_SWIZID_INIT              0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_BAR_LOCAL_SWIZID                    7:6 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_BAR_LOCAL_SWIZID_INIT               0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_BAR_LOCAL_SWIZID_ALL                0x0 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_BAR_LOCAL_SWIZID_ONE                0x1 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_BAR_LOCAL_SWIZID_GUEST              0x2 /* RW--V */
#define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_GUEST_VEID_MASK                   31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_GUEST_VEID_MASK_INIT                0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG(i)                         (0x001F9600+(i)*4) /* RW-4A */
#define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG__SIZE_1                                   128 /*       */
#define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG__PRIV_LEVEL_MASK                          0x001FAA54 /*       */
#define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG_REMOTE_SWIZID                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG_REMOTE_SWIZID_INIT                        0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG_LOCAL_SWIZID                              9:8 /* RWEVF */
#define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG_LOCAL_SWIZID_INIT                         0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG_LOCAL_SWIZID_ALL                          0x0 /* RW--V */
#define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG_LOCAL_SWIZID_ONE                          0x1 /* RW--V */
#define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG_LOCAL_SWIZID_GUEST                        0x2 /* RW--V */
#define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG_FAULT_ID                                24:16 /* RWXUF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOTTOM                                                                 0x001F9800 /* RW-4R */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOTTOM__PRIV_LEVEL_MASK              0x001FAA54 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOTTOM_PER_SLICE                                                             19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOTTOM_PER_SLICE_INIT                                                         0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_MIDDLE                                                                 0x001F9804 /* RW-4R */
#define NV_PFB_PRI_MMU_MEM_PARTITION_MIDDLE__PRIV_LEVEL_MASK              0x001FAA54 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE                                                             19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_INIT                                                         0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE                                                   4096 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE_LG2                                                0xC /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_ATOM_SIZE                               4096
#define NV_PFB_PRI_MMU_MEM_PARTITION_ATOM_SIZE_LG2                            0xC
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK                                      0x001F9814 /* RW-4R */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8     /* RW--V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  15 /* RW--V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1  0x0000884C /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP                         0x001F9808 /* RW-4R */
#define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP__PRIV_LEVEL_MASK   0x001F9814 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_ADDR                          23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_ADDR_INIT                      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_LOCALIZATION                 30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_LOCALIZATION_INIT              0x1 /* RWE-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_LOCALIZATION_DISABLE           0x0 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_LOCALIZATION_ENABLE            0x1 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_MODE                         31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_MODE_INIT                      0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_MODE_RELATIVE                  0x0 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_MODE_ABSOLUTE                  0x1 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_ADDR_ALIGNMENT                0x10
#define NV_PFB_PRI_MMU_MEM_PARTITION_ACTUAL_TOP                         0x001F9818 /* R--4R */
#define NV_PFB_PRI_MMU_MEM_PARTITION_ACTUAL_TOP_ADDR                          23:0 /* R--VF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_ACTUAL_TOP_ACTIVE                       31:31 /* R--VF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_ACTUAL_TOP_ADDR_ALIGNMENT                0x10
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG                         0x001F9810 /* RW-4R */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG__PRIV_LEVEL_MASK 0x001FAA54  /*       */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL                      6:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_INIT          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_ALL                           0x00 /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_HALF                          0x08 /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_QUARTER_0                     0x0A /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_QUARTER_1                     0x28 /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_EIGHTH_0                      0x0B /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_EIGHTH_1                      0x0E /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_EIGHTH_2                      0x38 /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_EIGHTH_3                      0x68 /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_H0_H1                         0x08 /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_H0_Q2_Q3                      0x28 /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_Q0_Q1_H1                      0x0A /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_H0_E4_E5_Q3                   0x38 /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_H0_Q2_E6_E7                   0x68 /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_Q0_E2_E3_H1                   0x0E /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_E0_E1_Q1_H1                   0x0B /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_H0_E4_E5_E6_E7                0x78 /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_E0_E1_E2_E3_H1                0x0F /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_Q0_Q1_Q2_Q3                   0x2A /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_Q0_Q1_Q2_E6_E7                0x6A /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_Q0_Q1_E4_E5_Q3                0x3A /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_Q0_E2_E3_Q2_Q3                0x2E /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_E0_E1_Q1_Q2_Q3                0x2B /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_Q0_Q1_E4_E5_E6_E7             0x7A /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_Q0_E2_E3_Q2_E6_E7             0x6E /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_Q0_E2_E3_E4_E5_Q3             0x3E /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_E0_E1_Q1_Q2_E6_E7             0x6B /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_E0_E1_Q1_E4_E5_Q3             0x3B /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_E0_E1_E2_E3_Q2_Q3             0x2F /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_Q0_E2_E3_E4_E5_E6_E7          0x7E /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_E0_E1_Q1_E4_E5_E6_E7          0x7B /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_E0_E1_E2_E3_Q2_E6_E7          0x6F /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_E0_E1_E2_E3_E4_E5_Q3          0x3F /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_VAL_E0_E1_E2_E3_E4_E5_E6_E7       0x7F /* RW--V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_MIN_GROUP_SIZE                   31:30 /* R-EVF */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_MIN_GROUP_SIZE_ALL          0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_MIN_GROUP_SIZE_HALF         0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_MIN_GROUP_SIZE_QUARTER      0x00000002 /* R-E-V */
#define NV_PFB_PRI_MMU_L2_TLB_BOUNDARY_CFG_MIN_GROUP_SIZE_EIGHTH       0x00000003 /* R---V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0                                                             0x001F980C /* RW-4R */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0__PRIV_LEVEL_MASK          0x001FAA54 /*       */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL                                                               10:0 /* RWEVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_INIT                                                    0x00000603 /* RWE-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_0                        0x603 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_1                        0x423 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_2                        0x621 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_3                        0x40B /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_4                        0x429 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_5                        0x4A1 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_6                        0x681 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_7                        0x407 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_8                        0x40D /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_9                        0x419 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_10                       0x431 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_11                       0x461 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_12                       0x4C1 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_13                       0x581 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_14                       0x701 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_LOCALIZATION                      20:20 /* RWEVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_LOCALIZATION_INIT                   0x0 /* RWE-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_LOCALIZATION_DISABLE                0x0 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_LOCALIZATION_ENABLE                 0x1 /* RW--V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_DIVISOR                           31:22 /* R-EVF */
#define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_DIVISOR_INIT                 0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_0                        0x603
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_1                        0x623
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_2                        0x623
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_3                        0x62B
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_4                        0x62B
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_5                        0x6A3
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_6                        0x6A3
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_7                        0x62F
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_8                        0x62F
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_9                        0x63B
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_10                       0x63B
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_11                       0x6E3
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_12                       0x6E3
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_13                       0x7A3
#define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_14                       0x7A3
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER(i)                     (0x001FAA80 + (i)*4) /* RW-4A */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1                8 /*       */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__PRIV_LEVEL_MASK    0x001FA9A8 /*       */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL                    31:0 /* RWEUF */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_INVALID            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB0             0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB1             0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB2             0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB3             0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB4             0x00000010 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB5             0x00000020 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB6             0x00000040 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB7             0x00000080 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB8             0x00000100 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB9             0x00000200 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB10            0x00000400 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB11            0x00000800 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB12            0x00001000 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB13            0x00002000 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB14            0x00004000 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB15            0x00008000 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_ALL_HSHUBS         0x0000001f /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_PCIE               1 /* RW--V */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_565MODE            2147483648 /*       */
#define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_464MODE            1073741824 /*       */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG                         0x001FAAA0 /* RW-4R */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG__PRIV_LEVEL_MASK        0x001FA9A8 /*       */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS                     31:0 /* RWEUF */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INVALID             0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB0         0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB1         0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB2         0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB3         0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB4         0x00000010 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB5         0x00000020 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB6         0x00000040 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB7         0x00000080 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB8         0x00000100 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB9         0x00000200 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB10        0x00000400 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB11        0x00000800 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB12        0x00001000 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB13        0x00002000 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB14        0x00004000 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB15        0x00008000 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_BOTH_HSHUBS         0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ALL_HSHUBS          0x0000001f /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_PCIE                1 /* RW--V */
#define NV_PFB_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INIT                1 /* RWE-V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT                                  0x001FA840 /* RW-4R */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_NUM_RANGE_CHECKER                0x00000008 /*       */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE                                    3:0 /* R-EVF */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE_INIT  2 /* R-E-V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE                          29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_CLEAR               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_SET                 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_MODE                                  30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_ACCESS                      0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_DIRTY                       0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_INIT                        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE                                31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_FALSE                     0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_TRUE                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_INIT                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO(i)         (0x001FA85C+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO__SIZE_1  8 /*       */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_GRANULARITY               3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_GRANULARITY_INIT   0x00000005 /* RWE-V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL                     31:24 /* RWEVF */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL_INIT           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI(i)         (0x001FA860+(i)*8) /* RW-4A */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI__SIZE_1  8 /*       */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL                      31:0 /* RWEVF */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL_INIT           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DUMP                             0x001FA844 /* RW-4R */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DUMP_TRIGGER                          31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DUMP_TRIGGER_FALSE               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DUMP_TRIGGER_TRUE                0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_LO                        0x001FA848 /* RW-4R */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_LO_ADDR                        31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_LO_ADDR_RESET             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_HI                        0x001FA84C /* RW-4R */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_HI_ADDR                         31:0 /* RWEVF */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_HI_ADDR_RESET             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE                      0x001FA850 /* RW-4R */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_VAL                        19:0 /* RWEVF */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_VAL_RESET            0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_ENABLE                    31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_ENABLE_FALSE         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_ENABLE_TRUE          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_ENABLE_INIT          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_PUT                       0x001FA854 /* R--4R */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_PUT_PTR                         19:0 /* R-EVF */
#define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_PUT_PTR_RESET             0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR                                   0x001FA858 /* RW-4R */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR__PRIV_LEVEL_MASK      0x001FA7D0 /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_VIDMEM                                   1:0 /* RWEVF */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_VIDMEM_IN_USE_DISABLED            0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_VIDMEM_PROTECTED_DISABLED         0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_VIDMEM_ENABLED                    0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_VIDMEM_DISABLED                   0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_ACCESS_COUNTER                           5:4 /* RWEVF */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_ACCESS_COUNTER_IN_USE_DISABLED    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_ACCESS_COUNTER_PROTECTED_DISABLED 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_ACCESS_COUNTER_ENABLED            0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_ACCESS_COUNTER_DISABLED           0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_SECURE_REQUEST                           6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_SECURE_REQUEST_DISABLED           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_SECURE_REQUEST_ENABLED            0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_SECURE_REQUEST_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK                                      0x001F981C /* RW-4R */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION                             3:0 /* RWEVF */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL   15 /* RWE-V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED   0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED  0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                      0:0 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                      1:1 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                      2:2 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                      3:3 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE        0x00000001 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE       0x00000000 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION                            7:4 /* RWEVF */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL        "mmu_plm" /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 12     /* RW--V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL  15 /* RW--V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED  0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0                     4:4 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1                     5:5 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2                     6:6 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3                     7:7 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE       0x00000001 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE      0x00000000 /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_VIOLATION                              8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION                             9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                       10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                      11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE                             31:12 /* RWEVF */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL                "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0   0x000FFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_PMU_ENABLED_FUSE1  0x0000884E /* RW--V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG                                       0x001F9820 /* RW-4R */
#define NV_PFB_PRI_MMU_POWERGATE_CFG__PRIV_LEVEL_MASK     0x001F981C /*       */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU                                      0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU_DISABLED                             0x0 /* RW--V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU_ENABLED                              0x1 /* RW--V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU_INIT                                 0x1 /* RWE-V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU_STATUS                               1:1 /* R-EVF */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU_STATUS_DISABLED                      0x0 /* R---V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU_STATUS_ENABLED                       0x1 /* R---V */
#define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU_STATUS_INIT                          0x0 /* R-E-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK                                 0x001FA390 /* RW-4R */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_CE                                     0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_CE_DISABLED                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_CE_ENABLED                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_DNISO                                  1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_DNISO_DISABLED                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_DNISO_ENABLED                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_FE                                     2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_FE_DISABLED                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_FE_ENABLED                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_FECS                                   3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_FECS_DISABLED                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_FECS_ENABLED                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_HOST                                   4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_HOST_DISABLED                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_HOST_ENABLED                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_HOST_CPU                               5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_HOST_CPU_DISABLED               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_HOST_CPU_ENABLED                0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_MMU                                    6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_MMU_DISABLED                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_MMU_ENABLED                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVDEC                                  7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVDEC_DISABLED                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVDEC_ENABLED                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_GSPLITE                                8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_GSPLITE_DISABLED                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_GSPLITE_ENABLED                 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_NISO                                   9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_NISO_DISABLED                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_NISO_ENABLED                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_P2P                                  10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_P2P_DISABLED                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_P2P_ENABLED                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_PD                                   11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_PD_DISABLED                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_PD_ENABLED                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_PERF                                 12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_PERF_DISABLED                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_PERF_ENABLED                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_PMU                                  13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_PMU_DISABLED                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_PMU_ENABLED                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_RASTERTWOD                           14:14 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_RASTERTWOD_DISABLED             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_RASTERTWOD_ENABLED              0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_SCC                                  15:15 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_SCC_DISABLED                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_SCC_ENABLED                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_SEC                                  16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_SEC_DISABLED                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_SEC_ENABLED                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_SSYNC                                17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_SSYNC_DISABLED                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_SSYNC_ENABLED                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_XV                                   18:18 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_XV_DISABLED                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_XV_ENABLED                      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVENC                                19:19 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVENC_DISABLED                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVENC_ENABLED                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_SKED                                 21:21 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_SKED_DISABLED                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_SKED_ENABLED                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_MFC                                  23:23 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_MFC_DISABLED                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_MFC_ENABLED                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_DWBIF                                24:24 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_DWBIF_DISABLED                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_DWBIF_ENABLED                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_FBFALCON                             25:25 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_FBFALCON_DISABLED               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_FBFALCON_ENABLED                0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_CE_SHIM                              26:26 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_CE_SHIM_DISABLED                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_CE_SHIM_ENABLED                 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_GSP                                  27:27 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_GSP_DISABLED                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_GSP_ENABLED                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVJPG                                28:28 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVJPG_DISABLED                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVJPG_ENABLED                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_OFA                                  29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_OFA_DISABLED                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_OFA_ENABLED                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_ESC                                  30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_ESC_DISABLED                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_ESC_ENABLED                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_FSP                                  31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_FSP_DISABLED                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_UNIT_MASK_FSP_ENABLED                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK                                  0x001FA394 /* RW-4R */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_RD                                      0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_RD_DISABLED                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_RD_ENABLED                       0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_WR                                      1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_WR_DISABLED                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_WR_ENABLED                       0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_GATOM                                   2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_GATOM_DISABLED                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_GATOM_ENABLED                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_GRED                                    3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_GRED_DISABLED                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_GRED_ENABLED                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_CACHE_MGMT                              4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_DISABLED              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_ENABLED               0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PREFETCH                                5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PREFETCH_DISABLED                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PREFETCH_ENABLED                 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH                            6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_DISABLED            0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_ENABLED             0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_MEMBAR                                  7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_MEMBAR_DISABLED                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_MEMBAR_ENABLED                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_RD                                 8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_RD_DISABLED                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_RD_ENABLED                  0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_WR                                 9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_WR_DISABLED                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_WR_ENABLED                  0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_GRED                            10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_GRED_DISABLED               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_GRED_ENABLED                0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_GATOM                            11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_DISABLED              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_ENABLED               0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PACK_RD                               12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PACK_RD_DISABLED                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PACK_RD_ENABLED                  0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_WR                             13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_WR_DISABLED               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_WR_ENABLED                0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_GRED                           14:14 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_DISABLED             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_ENABLED              0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM                          15:15 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_DISABLED            0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_ENABLED             0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_MULTICAST                             16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_MULTICAST_DISABLED               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_MULTICAST_ENABLED                0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_RDMC                                  17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_RDMC_DISABLED                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_RDMC_ENABLED                     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR                     18:18 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR_DISABLED       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR_ENABLED        0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED                   19:19 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED_DISABLED     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED_ENABLED      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM                  20:20 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM_DISABLED    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM_ENABLED     0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS                           22:22 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_DISABLED             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_ENABLED              0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS                          23:23 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_DISABLED            0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_ENABLED             0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_VIDMEM                                24:24 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_VIDMEM_ENABLED                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_VIDMEM_DISABLED                  0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PEER                                  25:25 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PEER_ENABLED                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_PEER_DISABLED                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_SYSMEM_C                              26:26 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_SYSMEM_C_ENABLED                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_SYSMEM_C_DISABLED                0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_SYSMEM_NC                             27:27 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_ENABLED                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_DISABLED               0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_TYPE                                  30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_TYPE_VIRTUAL                     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_TYPE_PHYSICAL                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_EXCLUSIVE                             31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_FALSE                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_TRUE                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL                                        0x001F9828 /* RW-4R */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL__PRIV_LEVEL_MASK               0x001FAA48 /*       */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE                         2:0 /* RWEVF */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_L2               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC           0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_RMW              0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_POWER            0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_PCIE             0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA                          4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA_OFF               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA_ON                0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE                       5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_L2             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_FOLLOW_SYS_COH 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32                                 8:8 /* RWEVF */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32_DISABLED                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32_ENABLED                  0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64                                 9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64_DISABLED                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64_ENABLED                  0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32                                    10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32_DISABLED                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32_ENABLED                       0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64                                    11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64_DISABLED                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64_ENABLED                       0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32                        12:12 /* RWEVF */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32_DISABLED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32_ENABLED           0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64                        13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64_DISABLED          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64_ENABLED           0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_INVALIDATE_SKIPPED_A                                         0x001F982C /* C--4R */
#define NV_PFB_PRI_MMU_INVALIDATE_SKIPPED_A_GFID                                          31:0 /* C--VF */
#define NV_PFB_PRI_MMU_INVALIDATE_SKIPPED_A_GFID_INIT                               0x00000000 /* C---V */
#define NV_PFB_PRI_MMU_INVALIDATE_SKIPPED_B                                         0x001F9830 /* C--4R */
#define NV_PFB_PRI_MMU_INVALIDATE_SKIPPED_B_GFID                                          31:0 /* C--VF */
#define NV_PFB_PRI_MMU_INVALIDATE_SKIPPED_B_GFID_INIT                               0x00000000 /* C---V */
#define NV_PFB_PRI_MMU_CC_CONFIG                                                                   0x001FA9B0 /* RW-4R */
#define NV_PFB_PRI_MMU_CC_CONFIG__PRIV_LEVEL_MASK                       0x001FA9A4 /*       */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_MODE                                                                  0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_MODE_DISABLED                                                  0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_MODE_ENABLED                                                   0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_ENABLE_FUSE                                                           1:1 /* R-EVF */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_ENABLE_FUSE_DISABLED                                           0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_ENABLE_FUSE_ENABLED                                            0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_CC_CONFIG_CPU_BAR1_TRUSTED                                                         2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CONFIG_CPU_BAR1_TRUSTED_DISABLED                                         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CONFIG_CPU_BAR1_TRUSTED_ENABLED                                          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CONFIG_SWIZID_CHECK                                                             3:3 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CONFIG_SWIZID_CHECK_DISABLED                                             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CONFIG_SWIZID_CHECK_ENABLED                                              0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CONFIG_ATS_FORCE_SWIZID_0                                                       4:4 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CONFIG_ATS_FORCE_SWIZID_0_ENABLED                                        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CONFIG_ATS_FORCE_SWIZID_0_DISABLED                                       0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CONFIG_TDISP_MODE                                                               5:5 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CONFIG_TDISP_MODE_DISABLED                                               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CONFIG_TDISP_MODE_ENABLED                                                0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CONFIG_TDISP_RESTRICT_SYSMEM_ACCESS                                             6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CONFIG_TDISP_RESTRICT_SYSMEM_ACCESS_FALSE                                0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CONFIG_TDISP_RESTRICT_SYSMEM_ACCESS_TRUE                                 0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CONFIG_NVLINK_ENCRYPTION                                                         7:7 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CONFIG_NVLINK_ENCRYPTION_DISABLED                                         0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CONFIG_NVLINK_ENCRYPTION_ENABLED                                          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_LOCK_FB                                                             29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_LOCK_FB_ENABLED                                                0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_LOCK_FB_INIT                                                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_LOCK_FB_DISABLED                                               0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_LOCK_HWPM                                                           30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_LOCK_HWPM_ENABLED                                              0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_LOCK_HWPM_INIT                                                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_LOCK_HWPM_DISABLED                                             0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_LOCK_MISC                                                           31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_LOCK_MISC_ENABLED                                              0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_LOCK_MISC_INIT                                                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_CONFIG_CC_LOCK_MISC_DISABLED                                             0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_UNTRUSTED                                                    0x00000000 /*       */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_CC_AWARE                                                     0x00000001 /*       */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_QUARANTINED                                                  0x00000002 /*       */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_TRUSTED                                                      0x00000003 /*       */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A                                                            0x001FA9B8 /* RW-4R */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A__PRIV_LEVEL_MASK                0x001FA9A4 /*       */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_NISO                                                              1:0 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_NISO_INIT                   0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_ISO                                                               3:2 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_ISO_INIT                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_DNISO                                                             5:4 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_DNISO_INIT                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_DWBIF                                                             7:6 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_DWBIF_INIT                    0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_NVDEC                                                             9:8 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_NVDEC_INIT                  0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_NVENC                                                           11:10 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_NVENC_INIT                  0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_NVJPG                                                           13:12 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_NVJPG_INIT                  0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_OFA                                                             15:14 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_OFA_INIT                    0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_GSP                                                             17:16 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_GSP_INIT                       0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_FSP                                                             19:18 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_FSP_INIT                       0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_SEC                                                             21:20 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_SEC_INIT                       0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_FBFALCON                                                        23:22 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_FBFALCON_INIT               0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_PMU                                                             25:24 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_PMU_INIT                    0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_PERF                                                            27:26 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_PERF_INIT                   0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_ESC                                                             29:28 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_ESC_INIT                       0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_GSPLITE                                                          31:30 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_A_GSPLITE_INIT                  0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B                                                            0x001FA9BC /* RW-4R */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B__PRIV_LEVEL_MASK                0x001FA9A4 /*       */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_CE                                                                1:0 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_CE_INIT                        0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_CE_SHIM                                                           3:2 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_CE_SHIM_INIT                0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_FECS                                                              5:4 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_FECS_INIT                   0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_GPCCS                                                             7:6 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_GPCCS_INIT                  0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_FE                                                                9:8 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_FE_INIT                     0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_SKED                                                            11:10 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_SKED_INIT                   0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_PD                                                              13:12 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_PD_INIT                     0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_SCC                                                             15:14 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_SCC_INIT                    0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_MFC                                                             17:16 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_MFC_INIT                    0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_GCC                                                             19:18 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_GCC_INIT                    0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_PE                                                              21:20 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_PE_INIT                     0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_ROP                                                             23:22 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_ROP_INIT                    0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_RAST                                                            25:24 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_RAST_INIT                   0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_TEX                                                             27:26 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_TEX_INIT                    0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_XV_XAL_CPU                                                      29:28 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_XV_XAL_CPU_INIT               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_P2P                                                             31:30 /* RWEVF */
#define NV_PFB_PRI_MMU_CC_TRUST_LEVEL_B_P2P_INIT                      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK(i)                                                                               (0x001FA9C0+(i)*4) /* RW-4A */
#define NV_PFB_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK__SIZE_1                                                         32 /*       */
#define NV_PFB_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK__PRIV_LEVEL_MASK                       0x001FA9A0 /*       */
#define NV_PFB_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK_BITMAP                                                                                     31:0 /* RWEVF */
#define NV_PFB_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK_BITMAP_INIT                                                                          0xFFFFFFFF /* RWE-V */
#define NV_PFB_PRI_MMU_CC_GFID_TEE_STATE_ENABLE(i)                                                            (0x001F8F20+(i)*4)   /* RW-4A */
#define NV_PFB_PRI_MMU_CC_GFID_TEE_STATE_ENABLE__SIZE_1                                           2   /*       */
#define NV_PFB_PRI_MMU_CC_GFID_TEE_STATE_ENABLE__PRIV_LEVEL_MASK            0x001F8F40   /*       */
#define NV_PFB_PRI_MMU_CC_GFID_TEE_STATE_ENABLE_BITMASK                                                                 31:0   /* RWEVF */
#define NV_PFB_PRI_MMU_CC_GFID_TEE_STATE_ENABLE_BITMASK_INIT                                                      0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_GFID_DISABLE(i)                                                              (0x001F8F28+(i)*4)   /* RW-4A */
#define NV_PFB_PRI_MMU_GFID_DISABLE__SIZE_1                                             2   /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE__PRIV_LEVEL_MASK                0x001F8F44   /*       */
#define NV_PFB_PRI_MMU_GFID_DISABLE_BITMASK                                                                   31:0   /* RWEVF */
#define NV_PFB_PRI_MMU_GFID_DISABLE_BITMASK_INIT                                                        0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_UNTRUSTED                                                    0x00000000 /*       */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_CC_AWARE                                                     0x00000001 /*       */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_QUARANTINED                                                  0x00000002 /*       */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_TRUSTED                                                      0x00000003 /*       */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A                                                                        0x001F8F30   /* RW-4R */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A__PRIV_LEVEL_MASK                     0x001FA9A4   /*       */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_NISO                                                                      1:0   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_NISO_INIT                     0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_ISO                                                                       3:2   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_ISO_INIT                      0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_DNISO                                                                     5:4   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_DNISO_INIT                    0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_DWBIF                                                                     7:6   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_DWBIF_INIT                    0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_NVDEC                                                                     9:8   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_NVDEC_INIT                    0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_NVENC                                                                   11:10   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_NVENC_INIT                    0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_NVJPG                                                                   13:12   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_NVJPG_INIT                    0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_OFA                                                                     15:14   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_OFA_INIT                      0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_GSP                                                                     17:16   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_GSP_INIT                       0x00000001   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_FSP                                                                     19:18   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_FSP_INIT                      0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_SEC                                                                     21:20   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_SEC_INIT                      0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_FBFALCON                                                                23:22   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_FBFALCON_INIT                 0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_PMU                                                                     25:24   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_PMU_INIT                      0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_PERF                                                                    27:26   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_PERF_INIT                     0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_ESC                                                                     29:28   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_ESC_INIT                      0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_GSPLITE                                                                 31:30   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_A_GSPLITE_INIT                  0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B                                                                        0x001F8F38   /* RW-4R */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B__PRIV_LEVEL_MASK                     0x001FA9A4   /*       */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_CE                                                                        1:0   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_CE_INIT                       0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_CE_SHIM                                                                   3:2   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_CE_SHIM_INIT                  0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_FECS                                                                      5:4   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_FECS_INIT                     0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_GPCCS                                                                     7:6   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_GPCCS_INIT                    0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_FE                                                                        9:8   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_FE_INIT                       0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_SKED                                                                    11:10   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_SKED_INIT                     0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_PD                                                                      13:12   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_PD_INIT                       0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_SCC                                                                     15:14   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_SCC_INIT                      0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_MFC                                                                     17:16   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_MFC_INIT                      0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_GCC                                                                     19:18   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_GCC_INIT                      0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_PE                                                                      21:20   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_PE_INIT                       0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_ROP                                                                     23:22   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_ROP_INIT                      0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_RAST                                                                    25:24   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_RAST_INIT                     0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_TEX                                                                     27:26   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_TEX_INIT                      0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_XV_XAL_CPU                                                              29:28   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_XV_XAL_CPU_INIT               0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_P2P                                                                     31:30   /* RWEVF */
#define NV_PFB_PRI_MMU_NON_TEE_TRUST_LEVEL_B_P2P_INIT                      0x00000000   /* RWE-V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL                                                                    0x001F8EE0 /* RW-4R */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL__PRIV_LEVEL_MASK       0x001F8EDC /*       */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_LOCK_FB                                                               0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_LOCK_FB_ENABLED                                                0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_LOCK_FB_DISABLED                                               0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_LOCK_FB_INIT                                                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_LOCK_HWPM                                                             1:1 /* RWEVF */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_LOCK_HWPM_ENABLED                                              0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_LOCK_HWPM_DISABLED                                             0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_LOCK_HWPM_INIT                                                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_LOCK_MISC                                                             2:2 /* RWEVF */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_LOCK_MISC_ENABLED                                              0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_LOCK_MISC_DISABLED                                             0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_ACCESS_LOCK_CTRL_LOCK_MISC_INIT                                                 0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CG                            0x001FA398 /* RW-4R */
#define NV_PFB_PRI_MMU_CG_IDLE_CG_DLY_CNT                   5:0 /* RWEVF */
#define NV_PFB_PRI_MMU_CG_IDLE_CG_DLY_CNT_HWINIT     0x00000002 /* RWE-V */
#define NV_PFB_PRI_MMU_CG_IDLE_CG_DLY_CNT__PROD      0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_CG_IDLE_CG_DLY_CNT__MIN_LIMIT 0x00000002 /*       */
#define NV_PFB_PRI_MMU_CG_IDLE_CG_EN                        6:6 /* RWEVF */
#define NV_PFB_PRI_MMU_CG_IDLE_CG_EN_ENABLED         0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CG_IDLE_CG_EN_DISABLED        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CG_IDLE_CG_EN__PROD           0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CG_STATE_CG_EN                       7:7 /*       */
#define NV_PFB_PRI_MMU_CG_STATE_CG_EN_ENABLED        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CG_STATE_CG_EN_DISABLED       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_STATE_CG_EN__PROD          0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_STALL_CG_DLY_CNT                 13:8 /*       */
#define NV_PFB_PRI_MMU_CG_STALL_CG_DLY_CNT_HWINIT    0x00000002 /*       */
#define NV_PFB_PRI_MMU_CG_STALL_CG_DLY_CNT__PROD     0x00000002 /*       */
#define NV_PFB_PRI_MMU_CG_STALL_CG_EN                     14:14 /* RWEVF */
#define NV_PFB_PRI_MMU_CG_STALL_CG_EN_ENABLED        0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CG_STALL_CG_EN_DISABLED       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CG_STALL_CG_EN__PROD          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CG_QUIESCENT_CG_EN                 15:15 /*       */
#define NV_PFB_PRI_MMU_CG_QUIESCENT_CG_EN_ENABLED    0x00000001 /*       */
#define NV_PFB_PRI_MMU_CG_QUIESCENT_CG_EN_DISABLED   0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_QUIESCENT_CG_EN__PROD      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_WAKEUP_DLY_CNT                  19:16 /* RWEVF */
#define NV_PFB_PRI_MMU_CG_WAKEUP_DLY_CNT_HWINIT      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CG_WAKEUP_DLY_CNT__PROD       0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CG_WAKEUP_DLY_CNT__MIN_LIMIT  0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_THROT_CLK_CNT                   23:20 /*       */
#define NV_PFB_PRI_MMU_CG_THROT_CLK_CNT_FULLSPEED    0x0000000f /*       */
#define NV_PFB_PRI_MMU_CG_THROT_CLK_CNT__PROD        0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_DI_DT_SKEW_VAL                  27:24 /*       */
#define NV_PFB_PRI_MMU_CG_DI_DT_SKEW_VAL_HWINIT      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_DI_DT_SKEW_VAL__PROD       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_THROT_CLK_EN                    28:28 /*       */
#define NV_PFB_PRI_MMU_CG_THROT_CLK_EN_ENABLED       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CG_THROT_CLK_EN_DISABLED      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_THROT_CLK_EN__PROD         0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_THROT_CLK_SW_OVER               29:29 /*       */
#define NV_PFB_PRI_MMU_CG_THROT_CLK_SW_OVER_EN       0x00000001 /*       */
#define NV_PFB_PRI_MMU_CG_THROT_CLK_SW_OVER_DIS      0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_THROT_CLK_SW_OVER__PROD    0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_PAUSE_CG_EN                     30:30 /*       */
#define NV_PFB_PRI_MMU_CG_PAUSE_CG_EN_ENABLED        0x00000001 /*       */
#define NV_PFB_PRI_MMU_CG_PAUSE_CG_EN_DISABLED       0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_PAUSE_CG_EN__PROD          0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_HALT_CG_EN                      31:31 /*       */
#define NV_PFB_PRI_MMU_CG_HALT_CG_EN_ENABLED         0x00000001 /*       */
#define NV_PFB_PRI_MMU_CG_HALT_CG_EN_DISABLED        0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG_HALT_CG_EN__PROD           0x00000000 /*       */
#define NV_PFB_PRI_MMU_CG1                             0x001FA39C /* RW-4R */
#define NV_PFB_PRI_MMU_CG1_MONITOR_CG_EN                      0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_CG1_MONITOR_CG_EN_ENABLED       0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CG1_MONITOR_CG_EN_DISABLED      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CG1_MONITOR_CG_EN__PROD         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CG1_SLCG                          11:1 /* RWEVF */
#define NV_PFB_PRI_MMU_CG1_SLCG_ENABLED                0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CG1_SLCG_DISABLED               0x000007FF /* RWE-V */
#define NV_PFB_PRI_MMU_CG1_SLCG__PROD                  0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PG                             0x001FA3A0 /* RW-4R */
#define NV_PFB_PRI_MMU_PG_IDLE_BLPG_DLY_CNT                  7:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PG_IDLE_BLPG_DLY_CNT_HWINIT    0x0000000A /* RWE-V */
#define NV_PFB_PRI_MMU_PG_ELPG_EN_OFFSET_CNT                15:8 /* RWEVF */
#define NV_PFB_PRI_MMU_PG_ELPG_EN_OFFSET_CNT_HWINIT   0x0000000A /* RWE-V */
#define NV_PFB_PRI_MMU_PG_IDLE_BLPG_EN                     16:16 /* RWEVF */
#define NV_PFB_PRI_MMU_PG_IDLE_BLPG_EN_ENABLED        0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PG_IDLE_BLPG_EN_DISABLED       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PG_DIS_EARLY_WUP                    17:17 /* RWEVF */
#define NV_PFB_PRI_MMU_PG_DIS_EARLY_WUP_ENABLED       0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PG_DIS_EARLY_WUP_DISABLED      0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PG_DEEP_ELPG_EN                    18:18 /* RWEVF */
#define NV_PFB_PRI_MMU_PG_DEEP_ELPG_EN_ENABLED       0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_PG_DEEP_ELPG_EN_DISABLED      0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PG_IDLE_ELPG_EN                     19:19 /* RWEVF */
#define NV_PFB_PRI_MMU_PG_IDLE_ELPG_EN_ENABLED        0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PG_IDLE_ELPG_EN_DISABLED       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PG_DIDT_DELAY                       23:20 /* RWEVF */
#define NV_PFB_PRI_MMU_PG_DIDT_DELAY_HWINIT           0x0000000A /* RWE-V */
#define NV_PFB_PRI_MMU_PG_RESET_DURATION                   26:24 /* RWEVF */
#define NV_PFB_PRI_MMU_PG_RESET_DURATION_HWINIT       0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_PG_CLAMP_DELAY                      29:27 /* RWEVF */
#define NV_PFB_PRI_MMU_PG_CLAMP_DELAY_HWINIT          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_PG_ZONE_OFF_MASK                    30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_PG_ZONE_OFF_MASK_HWINIT        0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_PG_SOFT_GATING_EN                   31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_PG_SOFT_GATING_EN_ENABLED      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PG_SOFT_GATING_EN_DISABLED     0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PG1                            0x001FA3FC /* RW-4R */
#define NV_PFB_PRI_MMU_PG1_ZONE_SEQ                         23:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PG1_ZONE_SEQ_HWINIT            0x00053977 /* RWE-V */
#define NV_PFB_PRI_MMU_PG1_ZONE_MASK                       31:24 /* RWEVF */
#define NV_PFB_PRI_MMU_PG1_ZONE_MASK_HWINIT           0x000000FF /* RWE-V */
#define NV_PFB_PRI_MMU_CTRL                                         0x001FA380 /* RW-4R */
#define NV_PFB_PRI_MMU_CTRL__PRIV_LEVEL_MASK               0x001FAA48 /*       */
#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE                                     0:0 /* RWEVF */
#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB                        0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB                         0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CTRL_COMP_FAULT                                     2:2 /*       */
#define NV_PFB_PRI_MMU_CTRL_COMP_FAULT_ENABLED                      0x00000001 /*       */
#define NV_PFB_PRI_MMU_CTRL_COMP_FAULT_DISABLED                     0x00000000 /*       */
#define NV_PFB_PRI_MMU_CTRL_MISS_GRAN                                      4:3 /* RWEVF */
#define NV_PFB_PRI_MMU_CTRL_MISS_GRAN_FULL                          0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CTRL_MISS_GRAN_HALF                          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_MISS_GRAN_QUARTER                       0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_MISS_GRAN_NO_PTE_COMP                   0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE                                     6:5 /* RWEVF */
#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_ON                           0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS           0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_OFF                          0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE                                 8:7 /* RWEVF */
#define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE_ON                       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE_EVICT_SMPG_PARTIALS      0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE_EVICT_ALL_PARTIALS       0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE_OFF                      0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_L2_SEND_MODE                                   9:9 /* RWEVF */
#define NV_PFB_PRI_MMU_CTRL_L2_SEND_MODE_ONE_PTE                    0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_L2_SEND_MODE_WHOLE_CL                   0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CTRL_WORK_CREATION_DISABLE                        10:10 /* RWEVF */
#define NV_PFB_PRI_MMU_CTRL_WORK_CREATION_DISABLE_FALSE             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CTRL_WORK_CREATION_DISABLE_TRUE              0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE                        11:11 /* RWEVF */
#define NV_PFB_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_FALSE             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_TRUE              0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_CLEAR                         13:13 /* RWEVF */
#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_CLEAR_FALSE              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_CLEAR_TRUE               0x00000001 /* RW--T */
#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR                               14:14 /* R-EVF */
#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_FALSE                    0x00000000 /* R-E-V */
#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_TRUE                     0x00000001 /* R---V */
#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY                               15:15 /* R-EVF */
#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY_FALSE                    0x00000000 /* R---V */
#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY_TRUE                     0x00000001 /* R-E-V */
#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE                               23:16 /* R-EVF */
#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE_INIT     32 /* R-E-V */
#define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE                       25:24 /* RWEVF */
#define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_L2               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC           0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_RMW              0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_POWER            0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA                        26:26 /* RWEVF */
#define NV_PFB_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_OFF               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_ON                0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE                     27:27 /* RWEVF */
#define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_L2             0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_FOLLOW_SYS_COH 0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_PHYS                                     29:28 /* RWEVF */
#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_PHYS_ON                           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_PHYS_EVICT_SMPG_PARTIALS          0x00000001 /* RWE-V */
#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_PHYS_EVICT_ALL_PARTIALS           0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_PHYS_OFF                          0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_PM                                           0x001FA384 /* RW-4R */
#define NV_PFB_PRI_MMU_PM__RESTORE_TYPE                              "PERFMON" /*       */
#define NV_PFB_PRI_MMU_PM_SELECT                                           8:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_00                             0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_01                             0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_02                             0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_03                             0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_04                             0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_05                             0x00000005 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_06                             0x00000006 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_07                             0x00000007 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_08                             0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_09                             0x00000009 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_0A                             0x0000000A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_0B                             0x0000000B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_0C                             0x0000000C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_0D                             0x0000000D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_0E                             0x0000000E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_0F                             0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_10                             0x00000010 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_11                             0x00000011 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_12                             0x00000012 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_13                             0x00000013 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_14                             0x00000014 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_15                             0x00000015 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_16                             0x00000016 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_17                             0x00000017 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_18                             0x00000018 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_19                             0x00000019 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A                             0x0000001A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B                             0x0000001B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C                             0x0000001C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D                             0x0000001D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E                             0x0000001E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F                             0x0000001F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_20                             0x00000020 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_21                             0x00000021 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_22                             0x00000022 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_23                             0x00000023 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_24                             0x00000024 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_25                             0x00000025 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_26                             0x00000026 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_27                             0x00000027 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_28                             0x00000028 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_29                             0x00000029 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_2A                             0x0000002A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_2B                             0x0000002B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_2C                             0x0000002C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_2D                             0x0000002D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_2E                             0x0000002E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_2F                             0x0000002F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_30                             0x00000030 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_31                             0x00000031 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_32                             0x00000032 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_33                             0x00000033 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_34                             0x00000034 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_35                             0x00000035 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_36                             0x00000036 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_37                             0x00000037 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_38                             0x00000038 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_39                             0x00000039 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_3A                             0x0000003A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_3B                             0x0000003B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_3C                             0x0000003C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_3D                             0x0000003D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_3E                             0x0000003E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_3F                             0x0000003F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_40                             0x00000040 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_41                             0x00000041 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_42                             0x00000042 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_43                             0x00000043 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_44                             0x00000044 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_45                             0x00000045 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_46                             0x00000046 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_47                             0x00000047 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_48                             0x00000048 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_49                             0x00000049 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_4A                             0x0000004A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_4B                             0x0000004B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_4C                             0x0000004C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_4D                             0x0000004D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_4E                             0x0000004E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_4F                             0x0000004F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_50                             0x00000050 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_51                             0x00000051 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_52                             0x00000052 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_53                             0x00000053 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_54                             0x00000054 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_55                             0x00000055 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_56                             0x00000056 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_57                             0x00000057 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_58                             0x00000058 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_59                             0x00000059 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_5A                             0x0000005A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_5B                             0x0000005B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_5C                             0x0000005C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_5D                             0x0000005D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_5E                             0x0000005E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_5F                             0x0000005F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_60                             0x00000060 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_61                             0x00000061 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_62                             0x00000062 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_63                             0x00000063 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_64                             0x00000064 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_65                             0x00000065 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_66                             0x00000066 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_67                             0x00000067 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_68                             0x00000068 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_69                             0x00000069 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_6A                             0x0000006A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_6B                             0x0000006B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_6C                             0x0000006C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_6D                             0x0000006D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_6E                             0x0000006E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_6F                             0x0000006F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_70                             0x00000070 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_71                             0x00000071 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_72                             0x00000072 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_73                             0x00000073 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_74                             0x00000074 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_75                             0x00000075 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_76                             0x00000076 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_77                             0x00000077 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_78                             0x00000078 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_79                             0x00000079 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_7A                             0x0000007A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_7B                             0x0000007B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_7C                             0x0000007C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_7D                             0x0000007D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_7E                             0x0000007E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_7F                             0x0000007F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_80                             0x00000080 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_81                             0x00000081 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_82                             0x00000082 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_83                             0x00000083 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_84                             0x00000084 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_85                             0x00000085 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_86                             0x00000086 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_87                             0x00000087 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_88                             0x00000088 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_89                             0x00000089 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_8A                             0x0000008A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_8B                             0x0000008B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_8C                             0x0000008C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_8D                             0x0000008D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_8E                             0x0000008E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_8F                             0x0000008F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_90                             0x00000090 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_91                             0x00000091 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_92                             0x00000092 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_93                             0x00000093 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_94                             0x00000094 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_95                             0x00000095 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_96                             0x00000096 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_97                             0x00000097 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_98                             0x00000098 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_99                             0x00000099 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_9A                             0x0000009A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_9B                             0x0000009B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_9C                             0x0000009C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_9D                             0x0000009D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_9E                             0x0000009E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_9F                             0x0000009F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_A0                             0x000000A0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_A1                             0x000000A1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_A2                             0x000000A2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_A3                             0x000000A3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_A4                             0x000000A4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_A5                             0x000000A5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_A6                             0x000000A6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_A7                             0x000000A7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_A8                             0x000000A8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_A9                             0x000000A9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_AA                             0x000000AA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_AB                             0x000000AB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_AC                             0x000000AC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_AD                             0x000000AD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_AE                             0x000000AE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_AF                             0x000000AF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_B0                             0x000000B0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_B1                             0x000000B1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_B2                             0x000000B2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_B3                             0x000000B3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_B4                             0x000000B4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_B5                             0x000000B5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_B6                             0x000000B6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_B7                             0x000000B7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_B8                             0x000000B8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_B9                             0x000000B9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_BA                             0x000000BA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_BB                             0x000000BB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_BC                             0x000000BC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_BD                             0x000000BD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_BE                             0x000000BE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_BF                             0x000000BF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_C0                             0x000000C0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_C1                             0x000000C1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_C2                             0x000000C2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_C3                             0x000000C3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_C4                             0x000000C4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_C5                             0x000000C5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_C6                             0x000000C6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_C7                             0x000000C7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_C8                             0x000000C8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_C9                             0x000000C9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_CA                             0x000000CA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_CB                             0x000000CB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_CC                             0x000000CC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_CD                             0x000000CD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_CE                             0x000000CE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_CF                             0x000000CF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_D0                             0x000000D0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_D1                             0x000000D1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_D2                             0x000000D2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_D3                             0x000000D3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_D4                             0x000000D4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_D5                             0x000000D5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_D6                             0x000000D6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_D7                             0x000000D7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_D8                             0x000000D8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_D9                             0x000000D9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_DA                             0x000000DA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_DB                             0x000000DB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_DC                             0x000000DC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_DD                             0x000000DD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_DE                             0x000000DE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_DF                             0x000000DF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_E0                             0x000000E0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_E1                             0x000000E1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_E2                             0x000000E2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_E3                             0x000000E3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_E4                             0x000000E4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_E5                             0x000000E5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_E6                             0x000000E6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_E7                             0x000000E7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_E8                             0x000000E8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_E9                             0x000000E9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_EA                             0x000000EA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_EB                             0x000000EB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_EC                             0x000000EC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_ED                             0x000000ED /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_EE                             0x000000EE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_EF                             0x000000EF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_F0                             0x000000F0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_F1                             0x000000F1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_F2                             0x000000F2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_F3                             0x000000F3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_F4                             0x000000F4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_F5                             0x000000F5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_F6                             0x000000F6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_F7                             0x000000F7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_F8                             0x000000F8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_F9                             0x000000F9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_FA                             0x000000FA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_FB                             0x000000FB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_FC                             0x000000FC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_FD                             0x000000FD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_STATIC_PATTERN_5_4_GROUP           0x000000FE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_STATIC_PATTERN_A_4_GROUP           0x000000FF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_FE                             0x000000FE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_FF                             0x000000FF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_100                            0x00000100 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_101                            0x00000101 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_102                            0x00000102 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_103                            0x00000103 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_104                            0x00000104 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_105                            0x00000105 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_106                            0x00000106 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_107                            0x00000107 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_108                            0x00000108 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_109                            0x00000109 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_10A                            0x0000010A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_10B                            0x0000010B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_10C                            0x0000010C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_10D                            0x0000010D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_10E                            0x0000010E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_10F                            0x0000010F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_110                            0x00000110 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_111                            0x00000111 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_112                            0x00000112 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_113                            0x00000113 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_114                            0x00000114 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_115                            0x00000115 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_116                            0x00000116 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_117                            0x00000117 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_118                            0x00000118 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_119                            0x00000119 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_11A                            0x0000011A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_11B                            0x0000011B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_11C                            0x0000011C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_11D                            0x0000011D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_11E                            0x0000011E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_11F                            0x0000011F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_120                            0x00000120 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_121                            0x00000121 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_122                            0x00000122 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_123                            0x00000123 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_124                            0x00000124 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_125                            0x00000125 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_126                            0x00000126 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_127                            0x00000127 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_128                            0x00000128 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_129                            0x00000129 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_12A                            0x0000012A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_12B                            0x0000012B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_12C                            0x0000012C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_12D                            0x0000012D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_12E                            0x0000012E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_12F                            0x0000012F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_130                            0x00000130 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_131                            0x00000131 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_132                            0x00000132 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_133                            0x00000133 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_134                            0x00000134 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_135                            0x00000135 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_136                            0x00000136 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_137                            0x00000137 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_138                            0x00000138 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_139                            0x00000139 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_13A                            0x0000013A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_13B                            0x0000013B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_13C                            0x0000013C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_13D                            0x0000013D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_13E                            0x0000013E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_13F                            0x0000013F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_140                            0x00000140 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_141                            0x00000141 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_142                            0x00000142 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_143                            0x00000143 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_144                            0x00000144 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_145                            0x00000145 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_146                            0x00000146 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_147                            0x00000147 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_148                            0x00000148 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_149                            0x00000149 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_14A                            0x0000014A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_14B                            0x0000014B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_14C                            0x0000014C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_14D                            0x0000014D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_14E                            0x0000014E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_14F                            0x0000014F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_150                            0x00000150 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_151                            0x00000151 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_152                            0x00000152 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_153                            0x00000153 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_154                            0x00000154 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_155                            0x00000155 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_156                            0x00000156 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_157                            0x00000157 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_158                            0x00000158 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_159                            0x00000159 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_15A                            0x0000015A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_15B                            0x0000015B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_15C                            0x0000015C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_15D                            0x0000015D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_15E                            0x0000015E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_15F                            0x0000015F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_160                            0x00000160 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_161                            0x00000161 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_162                            0x00000162 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_163                            0x00000163 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_164                            0x00000164 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_165                            0x00000165 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_166                            0x00000166 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_167                            0x00000167 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_168                            0x00000168 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_169                            0x00000169 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_16A                            0x0000016A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_16B                            0x0000016B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_16C                            0x0000016C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_16D                            0x0000016D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_16E                            0x0000016E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_16F                            0x0000016F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_170                            0x00000170 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_171                            0x00000171 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_172                            0x00000172 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_173                            0x00000173 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_174                            0x00000174 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_175                            0x00000175 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_176                            0x00000176 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_177                            0x00000177 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_178                            0x00000178 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_179                            0x00000179 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_17A                            0x0000017A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_17B                            0x0000017B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_17C                            0x0000017C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_17D                            0x0000017D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_17E                            0x0000017E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_17F                            0x0000017F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_180                            0x00000180 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_181                            0x00000181 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_182                            0x00000182 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_183                            0x00000183 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_184                            0x00000184 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_185                            0x00000185 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_186                            0x00000186 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_187                            0x00000187 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_188                            0x00000188 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_189                            0x00000189 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_18A                            0x0000018A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_18B                            0x0000018B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_18C                            0x0000018C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_18D                            0x0000018D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_18E                            0x0000018E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_18F                            0x0000018F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_190                            0x00000190 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_191                            0x00000191 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_192                            0x00000192 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_193                            0x00000193 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_194                            0x00000194 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_195                            0x00000195 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_196                            0x00000196 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_197                            0x00000197 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_198                            0x00000198 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_199                            0x00000199 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_19A                            0x0000019A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_19B                            0x0000019B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_19C                            0x0000019C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_19D                            0x0000019D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_19E                            0x0000019E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_19F                            0x0000019F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A0                            0x000001A0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A1                            0x000001A1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A2                            0x000001A2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A3                            0x000001A3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A4                            0x000001A4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A5                            0x000001A5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A6                            0x000001A6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A7                            0x000001A7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A8                            0x000001A8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A9                            0x000001A9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1AA                            0x000001AA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1AB                            0x000001AB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1AC                            0x000001AC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1AD                            0x000001AD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1AE                            0x000001AE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1AF                            0x000001AF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B0                            0x000001B0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B1                            0x000001B1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B2                            0x000001B2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B3                            0x000001B3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B4                            0x000001B4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B5                            0x000001B5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B6                            0x000001B6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B7                            0x000001B7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B8                            0x000001B8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B9                            0x000001B9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1BA                            0x000001BA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1BB                            0x000001BB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1BC                            0x000001BC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1BD                            0x000001BD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1BE                            0x000001BE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1BF                            0x000001BF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C0                            0x000001C0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C1                            0x000001C1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C2                            0x000001C2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C3                            0x000001C3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C4                            0x000001C4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C5                            0x000001C5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C6                            0x000001C6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C7                            0x000001C7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C8                            0x000001C8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C9                            0x000001C9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1CA                            0x000001CA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1CB                            0x000001CB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1CC                            0x000001CC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1CD                            0x000001CD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1CE                            0x000001CE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1CF                            0x000001CF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D0                            0x000001D0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D1                            0x000001D1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D2                            0x000001D2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D3                            0x000001D3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D4                            0x000001D4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D5                            0x000001D5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D6                            0x000001D6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D7                            0x000001D7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D8                            0x000001D8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D9                            0x000001D9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1DA                            0x000001DA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1DB                            0x000001DB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1DC                            0x000001DC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1DD                            0x000001DD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1DE                            0x000001DE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1DF                            0x000001DF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E0                            0x000001E0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E1                            0x000001E1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E2                            0x000001E2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E3                            0x000001E3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E4                            0x000001E4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E5                            0x000001E5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E6                            0x000001E6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E7                            0x000001E7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E8                            0x000001E8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E9                            0x000001E9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1EA                            0x000001EA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1EB                            0x000001EB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1EC                            0x000001EC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1ED                            0x000001ED /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1EE                            0x000001EE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1EF                            0x000001EF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F0                            0x000001F0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F1                            0x000001F1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F2                            0x000001F2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F3                            0x000001F3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F4                            0x000001F4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F5                            0x000001F5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F6                            0x000001F6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F7                            0x000001F7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F8                            0x000001F8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F9                            0x000001F9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1FA                            0x000001FA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1FB                            0x000001FB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1FC                            0x000001FC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1FD                            0x000001FD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1FE                            0x000001FE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_GRP_1FF                            0x000001FF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1                                    24:16 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_00                        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_01                        0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_02                        0x00000002 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_03                        0x00000003 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_04                        0x00000004 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_05                        0x00000005 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_06                        0x00000006 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_07                        0x00000007 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_08                        0x00000008 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_09                        0x00000009 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_0A                        0x0000000A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_0B                        0x0000000B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_0C                        0x0000000C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_0D                        0x0000000D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_0E                        0x0000000E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_0F                        0x0000000F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_10                        0x00000010 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_11                        0x00000011 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_12                        0x00000012 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_13                        0x00000013 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_14                        0x00000014 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_15                        0x00000015 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_16                        0x00000016 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_17                        0x00000017 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_18                        0x00000018 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_19                        0x00000019 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A                        0x0000001A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B                        0x0000001B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C                        0x0000001C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D                        0x0000001D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E                        0x0000001E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F                        0x0000001F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_20                        0x00000020 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_21                        0x00000021 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_22                        0x00000022 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_23                        0x00000023 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_24                        0x00000024 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_25                        0x00000025 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_26                        0x00000026 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_27                        0x00000027 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_28                        0x00000028 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_29                        0x00000029 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_2A                        0x0000002A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_2B                        0x0000002B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_2C                        0x0000002C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_2D                        0x0000002D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_2E                        0x0000002E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_2F                        0x0000002F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_30                        0x00000030 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_31                        0x00000031 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_32                        0x00000032 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_33                        0x00000033 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_34                        0x00000034 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_35                        0x00000035 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_36                        0x00000036 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_37                        0x00000037 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_38                        0x00000038 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_39                        0x00000039 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_3A                        0x0000003A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_3B                        0x0000003B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_3C                        0x0000003C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_3D                        0x0000003D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_3E                        0x0000003E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_3F                        0x0000003F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_40                        0x00000040 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_41                        0x00000041 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_42                        0x00000042 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_43                        0x00000043 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_44                        0x00000044 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_45                        0x00000045 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_46                        0x00000046 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_47                        0x00000047 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_48                        0x00000048 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_49                        0x00000049 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_4A                        0x0000004A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_4B                        0x0000004B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_4C                        0x0000004C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_4D                        0x0000004D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_4E                        0x0000004E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_4F                        0x0000004F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_50                        0x00000050 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_51                        0x00000051 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_52                        0x00000052 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_53                        0x00000053 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_54                        0x00000054 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_55                        0x00000055 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_56                        0x00000056 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_57                        0x00000057 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_58                        0x00000058 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_59                        0x00000059 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_5A                        0x0000005A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_5B                        0x0000005B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_5C                        0x0000005C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_5D                        0x0000005D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_5E                        0x0000005E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_5F                        0x0000005F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_60                        0x00000060 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_61                        0x00000061 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_62                        0x00000062 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_63                        0x00000063 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_64                        0x00000064 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_65                        0x00000065 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_66                        0x00000066 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_67                        0x00000067 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_68                        0x00000068 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_69                        0x00000069 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_6A                        0x0000006A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_6B                        0x0000006B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_6C                        0x0000006C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_6D                        0x0000006D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_6E                        0x0000006E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_6F                        0x0000006F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_70                        0x00000070 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_71                        0x00000071 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_72                        0x00000072 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_73                        0x00000073 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_74                        0x00000074 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_75                        0x00000075 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_76                        0x00000076 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_77                        0x00000077 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_78                        0x00000078 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_79                        0x00000079 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_7A                        0x0000007A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_7B                        0x0000007B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_7C                        0x0000007C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_7D                        0x0000007D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_7E                        0x0000007E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_7F                        0x0000007F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_80                        0x00000080 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_81                        0x00000081 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_82                        0x00000082 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_83                        0x00000083 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_84                        0x00000084 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_85                        0x00000085 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_86                        0x00000086 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_87                        0x00000087 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_88                        0x00000088 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_89                        0x00000089 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_8A                        0x0000008A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_8B                        0x0000008B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_8C                        0x0000008C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_8D                        0x0000008D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_8E                        0x0000008E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_8F                        0x0000008F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_90                        0x00000090 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_91                        0x00000091 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_92                        0x00000092 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_93                        0x00000093 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_94                        0x00000094 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_95                        0x00000095 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_96                        0x00000096 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_97                        0x00000097 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_98                        0x00000098 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_99                        0x00000099 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_9A                        0x0000009A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_9B                        0x0000009B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_9C                        0x0000009C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_9D                        0x0000009D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_9E                        0x0000009E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_9F                        0x0000009F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A0                        0x000000A0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A1                        0x000000A1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A2                        0x000000A2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A3                        0x000000A3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A4                        0x000000A4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A5                        0x000000A5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A6                        0x000000A6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A7                        0x000000A7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A8                        0x000000A8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A9                        0x000000A9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_AA                        0x000000AA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_AB                        0x000000AB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_AC                        0x000000AC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_AD                        0x000000AD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_AE                        0x000000AE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_AF                        0x000000AF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B0                        0x000000B0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B1                        0x000000B1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B2                        0x000000B2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B3                        0x000000B3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B4                        0x000000B4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B5                        0x000000B5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B6                        0x000000B6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B7                        0x000000B7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B8                        0x000000B8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B9                        0x000000B9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_BA                        0x000000BA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_BB                        0x000000BB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_BC                        0x000000BC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_BD                        0x000000BD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_BE                        0x000000BE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_BF                        0x000000BF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C0                        0x000000C0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C1                        0x000000C1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C2                        0x000000C2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C3                        0x000000C3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C4                        0x000000C4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C5                        0x000000C5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C6                        0x000000C6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C7                        0x000000C7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C8                        0x000000C8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C9                        0x000000C9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_CA                        0x000000CA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_CB                        0x000000CB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_CC                        0x000000CC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_CD                        0x000000CD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_CE                        0x000000CE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_CF                        0x000000CF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D0                        0x000000D0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D1                        0x000000D1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D2                        0x000000D2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D3                        0x000000D3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D4                        0x000000D4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D5                        0x000000D5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D6                        0x000000D6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D7                        0x000000D7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D8                        0x000000D8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D9                        0x000000D9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_DA                        0x000000DA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_DB                        0x000000DB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_DC                        0x000000DC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_DD                        0x000000DD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_DE                        0x000000DE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_DF                        0x000000DF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E0                        0x000000E0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E1                        0x000000E1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E2                        0x000000E2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E3                        0x000000E3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E4                        0x000000E4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E5                        0x000000E5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E6                        0x000000E6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E7                        0x000000E7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E8                        0x000000E8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E9                        0x000000E9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_EA                        0x000000EA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_EB                        0x000000EB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_EC                        0x000000EC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_ED                        0x000000ED /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_EE                        0x000000EE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_EF                        0x000000EF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F0                        0x000000F0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F1                        0x000000F1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F2                        0x000000F2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F3                        0x000000F3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F4                        0x000000F4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F5                        0x000000F5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F6                        0x000000F6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F7                        0x000000F7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F8                        0x000000F8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F9                        0x000000F9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_FA                        0x000000FA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_FB                        0x000000FB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_FC                        0x000000FC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_FD                        0x000000FD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_5_4_GROUP      0x000000FE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_A_4_GROUP      0x000000FF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_FE                        0x000000FE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_FF                        0x000000FF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_100                       0x00000100 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_101                       0x00000101 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_102                       0x00000102 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_103                       0x00000103 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_104                       0x00000104 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_105                       0x00000105 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_106                       0x00000106 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_107                       0x00000107 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_108                       0x00000108 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_109                       0x00000109 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_10A                       0x0000010A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_10B                       0x0000010B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_10C                       0x0000010C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_10D                       0x0000010D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_10E                       0x0000010E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_10F                       0x0000010F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_110                       0x00000110 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_111                       0x00000111 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_112                       0x00000112 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_113                       0x00000113 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_114                       0x00000114 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_115                       0x00000115 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_116                       0x00000116 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_117                       0x00000117 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_118                       0x00000118 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_119                       0x00000119 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_11A                       0x0000011A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_11B                       0x0000011B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_11C                       0x0000011C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_11D                       0x0000011D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_11E                       0x0000011E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_11F                       0x0000011F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_120                       0x00000120 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_121                       0x00000121 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_122                       0x00000122 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_123                       0x00000123 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_124                       0x00000124 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_125                       0x00000125 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_126                       0x00000126 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_127                       0x00000127 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_128                       0x00000128 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_129                       0x00000129 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_12A                       0x0000012A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_12B                       0x0000012B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_12C                       0x0000012C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_12D                       0x0000012D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_12E                       0x0000012E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_12F                       0x0000012F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_130                       0x00000130 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_131                       0x00000131 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_132                       0x00000132 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_133                       0x00000133 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_134                       0x00000134 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_135                       0x00000135 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_136                       0x00000136 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_137                       0x00000137 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_138                       0x00000138 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_139                       0x00000139 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_13A                       0x0000013A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_13B                       0x0000013B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_13C                       0x0000013C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_13D                       0x0000013D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_13E                       0x0000013E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_13F                       0x0000013F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_140                       0x00000140 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_141                       0x00000141 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_142                       0x00000142 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_143                       0x00000143 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_144                       0x00000144 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_145                       0x00000145 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_146                       0x00000146 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_147                       0x00000147 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_148                       0x00000148 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_149                       0x00000149 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_14A                       0x0000014A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_14B                       0x0000014B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_14C                       0x0000014C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_14D                       0x0000014D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_14E                       0x0000014E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_14F                       0x0000014F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_150                       0x00000150 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_151                       0x00000151 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_152                       0x00000152 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_153                       0x00000153 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_154                       0x00000154 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_155                       0x00000155 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_156                       0x00000156 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_157                       0x00000157 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_158                       0x00000158 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_159                       0x00000159 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_15A                       0x0000015A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_15B                       0x0000015B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_15C                       0x0000015C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_15D                       0x0000015D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_15E                       0x0000015E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_15F                       0x0000015F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_160                       0x00000160 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_161                       0x00000161 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_162                       0x00000162 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_163                       0x00000163 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_164                       0x00000164 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_165                       0x00000165 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_166                       0x00000166 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_167                       0x00000167 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_168                       0x00000168 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_169                       0x00000169 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_16A                       0x0000016A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_16B                       0x0000016B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_16C                       0x0000016C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_16D                       0x0000016D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_16E                       0x0000016E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_16F                       0x0000016F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_170                       0x00000170 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_171                       0x00000171 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_172                       0x00000172 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_173                       0x00000173 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_174                       0x00000174 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_175                       0x00000175 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_176                       0x00000176 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_177                       0x00000177 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_178                       0x00000178 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_179                       0x00000179 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_17A                       0x0000017A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_17B                       0x0000017B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_17C                       0x0000017C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_17D                       0x0000017D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_17E                       0x0000017E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_17F                       0x0000017F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_180                       0x00000180 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_181                       0x00000181 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_182                       0x00000182 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_183                       0x00000183 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_184                       0x00000184 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_185                       0x00000185 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_186                       0x00000186 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_187                       0x00000187 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_188                       0x00000188 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_189                       0x00000189 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_18A                       0x0000018A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_18B                       0x0000018B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_18C                       0x0000018C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_18D                       0x0000018D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_18E                       0x0000018E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_18F                       0x0000018F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_190                       0x00000190 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_191                       0x00000191 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_192                       0x00000192 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_193                       0x00000193 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_194                       0x00000194 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_195                       0x00000195 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_196                       0x00000196 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_197                       0x00000197 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_198                       0x00000198 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_199                       0x00000199 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_19A                       0x0000019A /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_19B                       0x0000019B /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_19C                       0x0000019C /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_19D                       0x0000019D /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_19E                       0x0000019E /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_19F                       0x0000019F /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A0                       0x000001A0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A1                       0x000001A1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A2                       0x000001A2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A3                       0x000001A3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A4                       0x000001A4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A5                       0x000001A5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A6                       0x000001A6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A7                       0x000001A7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A8                       0x000001A8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A9                       0x000001A9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1AA                       0x000001AA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1AB                       0x000001AB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1AC                       0x000001AC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1AD                       0x000001AD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1AE                       0x000001AE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1AF                       0x000001AF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B0                       0x000001B0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B1                       0x000001B1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B2                       0x000001B2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B3                       0x000001B3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B4                       0x000001B4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B5                       0x000001B5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B6                       0x000001B6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B7                       0x000001B7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B8                       0x000001B8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B9                       0x000001B9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1BA                       0x000001BA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1BB                       0x000001BB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1BC                       0x000001BC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1BD                       0x000001BD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1BE                       0x000001BE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1BF                       0x000001BF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C0                       0x000001C0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C1                       0x000001C1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C2                       0x000001C2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C3                       0x000001C3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C4                       0x000001C4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C5                       0x000001C5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C6                       0x000001C6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C7                       0x000001C7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C8                       0x000001C8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C9                       0x000001C9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1CA                       0x000001CA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1CB                       0x000001CB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1CC                       0x000001CC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1CD                       0x000001CD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1CE                       0x000001CE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1CF                       0x000001CF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D0                       0x000001D0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D1                       0x000001D1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D2                       0x000001D2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D3                       0x000001D3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D4                       0x000001D4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D5                       0x000001D5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D6                       0x000001D6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D7                       0x000001D7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D8                       0x000001D8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D9                       0x000001D9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1DA                       0x000001DA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1DB                       0x000001DB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1DC                       0x000001DC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1DD                       0x000001DD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1DE                       0x000001DE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1DF                       0x000001DF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E0                       0x000001E0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E1                       0x000001E1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E2                       0x000001E2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E3                       0x000001E3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E4                       0x000001E4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E5                       0x000001E5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E6                       0x000001E6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E7                       0x000001E7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E8                       0x000001E8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E9                       0x000001E9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1EA                       0x000001EA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1EB                       0x000001EB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1EC                       0x000001EC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1ED                       0x000001ED /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1EE                       0x000001EE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1EF                       0x000001EF /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F0                       0x000001F0 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F1                       0x000001F1 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F2                       0x000001F2 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F3                       0x000001F3 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F4                       0x000001F4 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F5                       0x000001F5 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F6                       0x000001F6 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F7                       0x000001F7 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F8                       0x000001F8 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F9                       0x000001F9 /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1FA                       0x000001FA /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1FB                       0x000001FB /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1FC                       0x000001FC /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1FD                       0x000001FD /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1FE                       0x000001FE /* RW--V */
#define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1FF                       0x000001FF /* RW--V */
#define NV_PFB_PRI_MMU_PM_ALT_INPUT                                      29:29 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_ALT_INPUT_DISABLE                         0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PM_ALT_INPUT_ENABLE                          0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_ALT_INPUT_INIT                            0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_BLK_ACT                                        30:30 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_BLK_ACT_DISABLE                           0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PM_BLK_ACT_ENABLE                            0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_BLK_ACT_INIT                              0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_ENABLE                                         31:31 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_ENABLE_DISABLE                            0x00000000 /* RW--V */
#define NV_PFB_PRI_MMU_PM_ENABLE_ENABLE                             0x00000001 /* RW--V */
#define NV_PFB_PRI_MMU_PM_ENABLE_INIT                               0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_ADDR_LOW                                  0x001FA388 /* RW-4R */
#define NV_PFB_PRI_MMU_PM_ADDR_LOW_BITS                                   31:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_ADDR_LOW_BITS_INIT                        0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_ADDR_LOW_ALIGNMENT                        0x00000008 /*       */
#define NV_PFB_PRI_MMU_PM_ADDR_HIGH                                 0x001FA38C /* RW-4R */
#define NV_PFB_PRI_MMU_PM_ADDR_HIGH_BITS                                  31:0 /* RWEVF */
#define NV_PFB_PRI_MMU_PM_ADDR_HIGH_BITS_INIT                       0x00000000 /* RWE-V */
#define NV_PFB_PRI_MMU_PM_ADDR_HIGH_ALIGNMENT                       0x00000008 /*       */
#define NV_PFB_HSMMU0                                               0x0000a3ff:0x0000a000 /* RW--D */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_ATOM_SIZE                                4096
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_ATOM_SIZE_LG2                             0xC
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_0                           0x603
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_1                           0x623
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_2                           0x623
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_3                           0x62B
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_4                           0x62B
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_5                           0x6A3
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_6                           0x6A3
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_7                           0x62F
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_8                           0x62F
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_9                           0x63B
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_10                          0x63B
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_11                          0x6E3
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_12                          0x6E3
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_13                          0x7A3
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_SWIZID_MASK_14                          0x7A3
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK                             0x0000a0d8 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION                    3:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0             0:0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1             1:1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2             2:2 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3             3:3 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION                   7:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0            4:4 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1            5:5 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2            6:6 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3            7:7 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION                     8:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR        0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON          0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION                    9:9 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR       0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON         0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL              10:10 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED        0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED        0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL             11:11 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED       0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED       0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_ENABLE                    31:12 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL                                             0x0000a080 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL__PRIV_LEVEL_MASK                            0x0000a0d8 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_VM_PG_SIZE                                         0:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_VM_PG_SIZE_128KB                                   0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_VM_PG_SIZE_64KB                                    0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_COMP_FAULT                                         2:2 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_COMP_FAULT_ENABLED                                 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_COMP_FAULT_DISABLED                                0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_MISS_GRAN                                          4:3 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_MISS_GRAN_FULL                                     0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_MISS_GRAN_HALF                                     0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_MISS_GRAN_QUARTER                                  0x2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_MISS_GRAN_NO_PTE_COMP                              0x3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE                                         6:5 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE_ON                                      0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS                     0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS                      0x2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE_OFF                                     0x3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_L2_SEND_MODE                                       9:9 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_L2_SEND_MODE_ONE_PTE                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_L2_SEND_MODE_WHOLE_CL                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE                           25:24 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_L2                          0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC                      0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_RMW                         0x2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_POWER                       0x3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA                            26:26 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_OFF                          0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_ON                           0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE_PHYS                                  29:28 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE_PHYS_ON                                 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE_PHYS_EVICT_SMPG_PARTIALS                0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE_PHYS_EVICT_ALL_PARTIALS                 0x2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE_PHYS_OFF                                0x3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL                                         0x0000a0a0 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_UTLB_SIZE                                      1:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_UTLB_SIZE_INIT                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_UTLB_RB_SIZE                                   3:2 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_UTLB_RB_SIZE_INIT                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_SIZE                                 5:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_SIZE_INIT                            0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_FA_SIZE                              7:6 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_FA_SIZE_INIT                         0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_RB_SIZE                              9:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_RB_SIZE_INIT                         0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_BIG_PG                   11:10 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_BIG_PG_INIT                0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_SMALL_PG                 13:12 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_SMALL_PG_INIT              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_UTLB_SIZE                                15:14 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_UTLB_SIZE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_SIZE                                   17:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_SIZE_INIT                                0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_FA_SIZE                                19:18 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_FA_SIZE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_RB_SIZE                                21:20 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_RB_SIZE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_BIG_PG                       23:22 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_BIG_PG_INIT                    0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_SMALL_PG                     25:24 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_SMALL_PG_INIT                  0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE                      26:26 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE_FALSE                  0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE_TRUE                   0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE                       27:27 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE_FALSE                   0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE_TRUE                    0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_UTLB_RB_SIZE                             29:28 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_UTLB_RB_SIZE_INIT                          0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_SECURE_LOCK                                  30:30 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_SECURE_LOCK_FALSE                              0x0 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_SECURE_LOCK_INIT                               0x0 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_SECURE_LOCK_TRUE                               0x1 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE                    31:31 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE_TRUE                 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE_FALSE                0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_MISC                                         0x0000a0a8 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_MISC_UTLB_UF                                        2:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_MISC_UTLB_UF_INIT                                   0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_MISC_L1TLB_UF                                       5:3 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_MISC_L1TLB_UF_INIT                                  0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_MISC_NVL_UTLB_UF                                    8:6 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_MISC_NVL_UTLB_UF_INIT                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_MISC_NVL_L1TLB_UF                                  11:9 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_TLB_MISC_NVL_L1TLB_UF_INIT                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CAPABILITIES                                     0x0000a0ac /* R--4R */
#define NV_PFB_HSMMU0_PRI_MMU_CAPABILITIES_CE                                         0:0 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_CAPABILITIES_CE_YES                                     0x1 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_CAPABILITIES_CE_NO                                      0x0 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_CAPABILITIES_NVLINK                                     1:1 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_CAPABILITIES_NVLINK_YES                                 0x1 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_CAPABILITIES_NVLINK_NO                                  0x0 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_CAPABILITIES_CHI                                        2:2 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_CAPABILITIES_CHI_YES                                    0x1 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_CAPABILITIES_CHI_NO                                     0x0 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_CAPABILITIES_PCIE                                       3:3 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_CAPABILITIES_PCIE_YES                                   0x1 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_CAPABILITIES_PCIE_NO                                    0x0 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH                                         0x0000a0a4 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_DISABLE                                  0:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_DISABLE_FALSE                            0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_DISABLE_TRUE                             0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_BIG_DISABLE                                    1:1 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_BIG_DISABLE_FALSE                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_BIG_DISABLE_TRUE                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_UNFILLED_DISABLE                               2:2 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_UNFILLED_DISABLE_FALSE                         0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_UNFILLED_DISABLE_TRUE                          0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_ENABLE                                         3:3 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_ENABLE_TRUE                                    0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_INCR_ONLY                                      4:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_INCR_ONLY_FALSE                                0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_INCR_ONLY_TRUE                                 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL                             5:5 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL_FALSE                       0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL_TRUE                        0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_ATSGPA_DISABLE                                 6:6 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_ATSGPA_DISABLE_FALSE                           0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_ATSGPA_DISABLE_TRUE                            0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE                               7:7 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE_FALSE                         0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE_TRUE                          0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH                           12:12 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_DISABLE                     0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_ENABLE                      0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE                         15:13 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_1                         0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_2                         0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_4                         0x2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_8                         0x3 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_16                        0x4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_32                        0x5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_64                        0x6 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE                            16:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE_FALSE                        0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE_TRUE                         0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_BIG_DISABLE                              17:17 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_BIG_DISABLE_FALSE                          0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_BIG_DISABLE_TRUE                           0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE                         18:18 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE_FALSE                     0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE_TRUE                      0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_ENABLE                                   19:19 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_ENABLE_TRUE                                0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_INCR_ONLY                                20:20 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_INCR_ONLY_FALSE                            0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_INCR_ONLY_TRUE                             0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PREF_ON_FILL                       21:21 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PREF_ON_FILL_FALSE                   0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PREF_ON_FILL_TRUE                    0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_ATSGPA_DISABLE                           22:22 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_ATSGPA_DISABLE_FALSE                       0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_ATSGPA_DISABLE_TRUE                        0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SRIOVGPA_DISABLE                         23:23 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SRIOVGPA_DISABLE_FALSE                     0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SRIOVGPA_DISABLE_TRUE                      0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH                       28:28 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH_DISABLE                 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH_ENABLE                  0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE                     31:29 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_1                     0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_2                     0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_4                     0x2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_8                     0x3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_16                    0x4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_32                    0x5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_64                    0x6 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL                                       0x0000a0c4 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_WR_KIND                                      7:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_WR_KIND_INIT                                0x00 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_RD_KIND                                     15:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_RD_KIND_INIT                                0x00 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_DEBUG                                      16:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_DEBUG_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_DEBUG_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_PAGE_SIZE                                  18:17 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_4KB                                0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_64KB                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_128KB                              0x2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_1MB                                0x3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR                                         0x0000a0c8 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_APERTURE                                       1:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_APERTURE_PEER_MEM                              0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_C                             0x2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_NC                            0x3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_VOL                                            2:2 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_VOL_FALSE                                      0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_VOL_TRUE                                       0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_ADDR                                          31:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_ADDR_INIT                                0x0000000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT                           0x000000c /*       */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD                                         0x0000a0cc /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_APERTURE                                       1:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_APERTURE_PEER_MEM                              0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_C                             0x2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_NC                            0x3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_VOL                                            2:2 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_VOL_FALSE                                      0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_VOL_TRUE                                       0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_ADDR                                          31:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_ADDR_INIT                                0x0000000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT                           0x000000c /*       */
#define NV_PFB_HSMMU0_PRI_MMU_PM                                               0x0000a084 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT                                               7:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_00                                       0x00 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_01                                       0x01 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_02                                       0x02 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_03                                       0x03 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_04                                       0x04 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_05                                       0x05 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_06                                       0x06 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_07                                       0x07 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_08                                       0x08 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_09                                       0x09 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_0A                                       0x0a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_0B                                       0x0b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_0C                                       0x0c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_0D                                       0x0d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_0E                                       0x0e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_0F                                       0x0f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_10                                       0x10 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_11                                       0x11 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_12                                       0x12 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_13                                       0x13 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_14                                       0x14 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_15                                       0x15 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_16                                       0x16 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_17                                       0x17 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_18                                       0x18 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_19                                       0x19 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_1A                                       0x1a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_1B                                       0x1b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_1C                                       0x1c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_1D                                       0x1d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_1E                                       0x1e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_1F                                       0x1f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_20                                       0x20 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_21                                       0x21 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_22                                       0x22 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_23                                       0x23 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_24                                       0x24 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_25                                       0x25 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_26                                       0x26 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_27                                       0x27 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_28                                       0x28 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_29                                       0x29 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_2A                                       0x2a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_2B                                       0x2b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_2C                                       0x2c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_2D                                       0x2d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_2E                                       0x2e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_2F                                       0x2f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_30                                       0x30 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_31                                       0x31 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_32                                       0x32 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_33                                       0x33 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_34                                       0x34 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_35                                       0x35 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_36                                       0x36 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_37                                       0x37 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_38                                       0x38 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_39                                       0x39 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_3A                                       0x3a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_3B                                       0x3b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_3C                                       0x3c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_3D                                       0x3d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_3E                                       0x3e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_3F                                       0x3f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_40                                       0x40 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_41                                       0x41 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_42                                       0x42 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_43                                       0x43 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_44                                       0x44 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_45                                       0x45 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_46                                       0x46 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_47                                       0x47 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_48                                       0x48 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_49                                       0x49 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_4A                                       0x4a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_4B                                       0x4b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_4C                                       0x4c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_4D                                       0x4d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_4E                                       0x4e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_4F                                       0x4f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_50                                       0x50 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_51                                       0x51 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_52                                       0x52 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_53                                       0x53 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_54                                       0x54 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_55                                       0x55 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_56                                       0x56 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_57                                       0x57 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_58                                       0x58 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_59                                       0x59 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_5A                                       0x5a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_5B                                       0x5b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_5C                                       0x5c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_5D                                       0x5d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_5E                                       0x5e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_5F                                       0x5f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_60                                       0x60 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_61                                       0x61 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_62                                       0x62 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_63                                       0x63 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_64                                       0x64 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_65                                       0x65 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_66                                       0x66 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_67                                       0x67 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_68                                       0x68 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_69                                       0x69 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_6A                                       0x6a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_6B                                       0x6b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_6C                                       0x6c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_6D                                       0x6d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_6E                                       0x6e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_6F                                       0x6f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_70                                       0x70 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_71                                       0x71 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_72                                       0x72 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_73                                       0x73 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_74                                       0x74 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_75                                       0x75 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_76                                       0x76 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_77                                       0x77 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_78                                       0x78 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_79                                       0x79 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_7A                                       0x7a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_7B                                       0x7b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_7C                                       0x7c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_7D                                       0x7d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_7E                                       0x7e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_7F                                       0x7f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_80                                       0x80 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_81                                       0x81 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_82                                       0x82 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_83                                       0x83 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_84                                       0x84 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_85                                       0x85 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_86                                       0x86 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_87                                       0x87 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_88                                       0x88 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_89                                       0x89 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_8A                                       0x8a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_8B                                       0x8b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_8C                                       0x8c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_8D                                       0x8d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_8E                                       0x8e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_8F                                       0x8f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_90                                       0x90 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_91                                       0x91 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_92                                       0x92 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_93                                       0x93 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_94                                       0x94 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_95                                       0x95 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_96                                       0x96 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_97                                       0x97 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_98                                       0x98 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_99                                       0x99 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_9A                                       0x9a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_9B                                       0x9b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_9C                                       0x9c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_9D                                       0x9d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_9E                                       0x9e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_9F                                       0x9f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A0                                       0xa0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A1                                       0xa1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A2                                       0xa2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A3                                       0xa3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A4                                       0xa4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A5                                       0xa5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A6                                       0xa6 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A7                                       0xa7 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A8                                       0xa8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A9                                       0xa9 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_AA                                       0xaa /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_AB                                       0xab /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_AC                                       0xac /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_AD                                       0xad /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_AE                                       0xae /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_AF                                       0xaf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B0                                       0xb0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B1                                       0xb1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B2                                       0xb2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B3                                       0xb3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B4                                       0xb4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B5                                       0xb5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B6                                       0xb6 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B7                                       0xb7 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B8                                       0xb8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B9                                       0xb9 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_BA                                       0xba /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_BB                                       0xbb /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_BC                                       0xbc /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_BD                                       0xbd /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_BE                                       0xbe /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_BF                                       0xbf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C0                                       0xc0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C1                                       0xc1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C2                                       0xc2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C3                                       0xc3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C4                                       0xc4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C5                                       0xc5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C6                                       0xc6 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C7                                       0xc7 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C8                                       0xc8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C9                                       0xc9 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_CA                                       0xca /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_CB                                       0xcb /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_CC                                       0xcc /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_CD                                       0xcd /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_CE                                       0xce /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_CF                                       0xcf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D0                                       0xd0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D1                                       0xd1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D2                                       0xd2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D3                                       0xd3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D4                                       0xd4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D5                                       0xd5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D6                                       0xd6 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D7                                       0xd7 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D8                                       0xd8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D9                                       0xd9 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_DA                                       0xda /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_DB                                       0xdb /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_DC                                       0xdc /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_DD                                       0xdd /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_DE                                       0xde /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_DF                                       0xdf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E0                                       0xe0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E1                                       0xe1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E2                                       0xe2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E3                                       0xe3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E4                                       0xe4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E5                                       0xe5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E6                                       0xe6 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E7                                       0xe7 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E8                                       0xe8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E9                                       0xe9 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_EA                                       0xea /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_EB                                       0xeb /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_EC                                       0xec /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_ED                                       0xed /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_EE                                       0xee /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_EF                                       0xef /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F0                                       0xf0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F1                                       0xf1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F2                                       0xf2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F3                                       0xf3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F4                                       0xf4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F5                                       0xf5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F6                                       0xf6 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F7                                       0xf7 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F8                                       0xf8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F9                                       0xf9 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_FA                                       0xfa /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_FB                                       0xfb /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_FC                                       0xfc /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_FD                                       0xfd /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_STATIC_PATTERN_5_4_GROUP                     0xfe /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_STATIC_PATTERN_A_4_GROUP                     0xff /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1                                         15:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_00                                  0x00 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_01                                  0x01 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_02                                  0x02 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_03                                  0x03 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_04                                  0x04 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_05                                  0x05 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_06                                  0x06 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_07                                  0x07 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_08                                  0x08 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_09                                  0x09 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_0A                                  0x0a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_0B                                  0x0b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_0C                                  0x0c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_0D                                  0x0d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_0E                                  0x0e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_0F                                  0x0f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_10                                  0x10 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_11                                  0x11 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_12                                  0x12 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_13                                  0x13 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_14                                  0x14 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_15                                  0x15 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_16                                  0x16 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_17                                  0x17 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_18                                  0x18 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_19                                  0x19 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_1A                                  0x1a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_1B                                  0x1b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_1C                                  0x1c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_1D                                  0x1d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_1E                                  0x1e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_1F                                  0x1f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_20                                  0x20 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_21                                  0x21 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_22                                  0x22 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_23                                  0x23 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_24                                  0x24 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_25                                  0x25 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_26                                  0x26 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_27                                  0x27 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_28                                  0x28 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_29                                  0x29 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_2A                                  0x2a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_2B                                  0x2b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_2C                                  0x2c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_2D                                  0x2d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_2E                                  0x2e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_2F                                  0x2f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_30                                  0x30 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_31                                  0x31 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_32                                  0x32 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_33                                  0x33 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_34                                  0x34 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_35                                  0x35 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_36                                  0x36 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_37                                  0x37 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_38                                  0x38 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_39                                  0x39 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_3A                                  0x3a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_3B                                  0x3b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_3C                                  0x3c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_3D                                  0x3d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_3E                                  0x3e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_3F                                  0x3f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_40                                  0x40 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_41                                  0x41 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_42                                  0x42 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_43                                  0x43 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_44                                  0x44 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_45                                  0x45 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_46                                  0x46 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_47                                  0x47 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_48                                  0x48 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_49                                  0x49 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_4A                                  0x4a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_4B                                  0x4b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_4C                                  0x4c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_4D                                  0x4d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_4E                                  0x4e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_4F                                  0x4f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_50                                  0x50 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_51                                  0x51 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_52                                  0x52 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_53                                  0x53 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_54                                  0x54 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_55                                  0x55 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_56                                  0x56 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_57                                  0x57 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_58                                  0x58 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_59                                  0x59 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_5A                                  0x5a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_5B                                  0x5b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_5C                                  0x5c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_5D                                  0x5d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_5E                                  0x5e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_5F                                  0x5f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_60                                  0x60 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_61                                  0x61 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_62                                  0x62 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_63                                  0x63 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_64                                  0x64 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_65                                  0x65 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_66                                  0x66 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_67                                  0x67 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_68                                  0x68 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_69                                  0x69 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_6A                                  0x6a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_6B                                  0x6b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_6C                                  0x6c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_6D                                  0x6d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_6E                                  0x6e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_6F                                  0x6f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_70                                  0x70 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_71                                  0x71 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_72                                  0x72 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_73                                  0x73 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_74                                  0x74 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_75                                  0x75 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_76                                  0x76 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_77                                  0x77 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_78                                  0x78 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_79                                  0x79 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_7A                                  0x7a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_7B                                  0x7b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_7C                                  0x7c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_7D                                  0x7d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_7E                                  0x7e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_7F                                  0x7f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_80                                  0x80 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_81                                  0x81 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_82                                  0x82 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_83                                  0x83 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_84                                  0x84 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_85                                  0x85 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_86                                  0x86 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_87                                  0x87 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_88                                  0x88 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_89                                  0x89 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_8A                                  0x8a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_8B                                  0x8b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_8C                                  0x8c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_8D                                  0x8d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_8E                                  0x8e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_8F                                  0x8f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_90                                  0x90 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_91                                  0x91 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_92                                  0x92 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_93                                  0x93 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_94                                  0x94 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_95                                  0x95 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_96                                  0x96 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_97                                  0x97 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_98                                  0x98 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_99                                  0x99 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_9A                                  0x9a /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_9B                                  0x9b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_9C                                  0x9c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_9D                                  0x9d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_9E                                  0x9e /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_9F                                  0x9f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A0                                  0xa0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A1                                  0xa1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A2                                  0xa2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A3                                  0xa3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A4                                  0xa4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A5                                  0xa5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A6                                  0xa6 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A7                                  0xa7 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A8                                  0xa8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A9                                  0xa9 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_AA                                  0xaa /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_AB                                  0xab /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_AC                                  0xac /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_AD                                  0xad /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_AE                                  0xae /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_AF                                  0xaf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B0                                  0xb0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B1                                  0xb1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B2                                  0xb2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B3                                  0xb3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B4                                  0xb4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B5                                  0xb5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B6                                  0xb6 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B7                                  0xb7 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B8                                  0xb8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B9                                  0xb9 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_BA                                  0xba /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_BB                                  0xbb /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_BC                                  0xbc /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_BD                                  0xbd /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_BE                                  0xbe /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_BF                                  0xbf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C0                                  0xc0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C1                                  0xc1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C2                                  0xc2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C3                                  0xc3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C4                                  0xc4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C5                                  0xc5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C6                                  0xc6 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C7                                  0xc7 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C8                                  0xc8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C9                                  0xc9 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_CA                                  0xca /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_CB                                  0xcb /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_CC                                  0xcc /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_CD                                  0xcd /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_CE                                  0xce /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_CF                                  0xcf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D0                                  0xd0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D1                                  0xd1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D2                                  0xd2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D3                                  0xd3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D4                                  0xd4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D5                                  0xd5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D6                                  0xd6 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D7                                  0xd7 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D8                                  0xd8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D9                                  0xd9 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_DA                                  0xda /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_DB                                  0xdb /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_DC                                  0xdc /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_DD                                  0xdd /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_DE                                  0xde /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_DF                                  0xdf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E0                                  0xe0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E1                                  0xe1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E2                                  0xe2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E3                                  0xe3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E4                                  0xe4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E5                                  0xe5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E6                                  0xe6 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E7                                  0xe7 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E8                                  0xe8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E9                                  0xe9 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_EA                                  0xea /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_EB                                  0xeb /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_EC                                  0xec /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_ED                                  0xed /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_EE                                  0xee /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_EF                                  0xef /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F0                                  0xf0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F1                                  0xf1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F2                                  0xf2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F3                                  0xf3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F4                                  0xf4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F5                                  0xf5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F6                                  0xf6 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F7                                  0xf7 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F8                                  0xf8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F9                                  0xf9 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_FA                                  0xfa /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_FB                                  0xfb /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_FC                                  0xfc /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_FD                                  0xfd /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_5_4_GROUP                0xfe /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_A_4_GROUP                0xff /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_BLK_ACT                                            30:30 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_BLK_ACT_DISABLE                                      0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_BLK_ACT_ENABLE                                       0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_BLK_ACT_INIT                                         0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_ENABLE                                             31:31 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_ENABLE_DISABLE                                       0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_ENABLE_ENABLE                                        0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_ENABLE_INIT                                          0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_LOW                                      0x0000a088 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_LOW_ALIGNMENT                            0x00000008 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_LOW_BITS                                       31:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_LOW_BITS_INIT                            0x00000000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UPPER_ADDR_LOW                                0x0000a08c /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UPPER_ADDR_LOW_BITS                                 23:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UPPER_ADDR_LOW_BITS_INIT                        0x000000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_HIGH                                     0x0000a090 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_HIGH_ALIGNMENT                           0x00000008 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_HIGH_BITS                                      31:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_HIGH_BITS_INIT                           0x00000000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UPPER_ADDR_HIGH                               0x0000a094 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS                                23:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS_INIT                       0x000000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK                                     0x0000a098 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE0                                        0:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE0_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE0_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE1                                        1:1 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE1_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE1_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE2                                        2:2 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE2_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE2_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE3                                        3:3 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE3_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE3_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE4                                        4:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE4_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE4_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE5                                        5:5 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE5_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE5_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE6                                        6:6 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE6_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE6_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE7                                        7:7 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE7_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE7_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE8                                        8:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE8_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE8_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE9                                        9:9 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE9_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE9_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE10                                     10:10 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE10_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE10_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE11                                     11:11 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE11_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE11_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE12                                     12:12 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE12_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE12_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE13                                     13:13 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE13_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE13_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE14                                     14:14 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE14_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE14_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE15                                     15:15 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE15_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE15_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL0                                     16:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL0_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL0_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL1                                     17:17 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL1_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL1_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL2                                     18:18 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL2_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL2_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL3                                     19:19 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL3_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL3_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL4                                     20:20 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL4_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL4_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL5                                     21:21 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL5_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL5_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL6                                     22:22 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL6_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL6_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL7                                     23:23 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL7_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL7_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL8                                     24:24 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL8_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL8_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL9                                     25:25 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL9_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL9_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL10                                    26:26 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL10_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL10_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL11                                    27:27 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL11_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL11_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL12                                    28:28 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL12_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL12_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL13                                    29:29 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL13_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL13_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL14                                    30:30 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL14_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL14_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL15                                    31:31 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL15_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL15_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK                                      0x0000a09c /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_RD                                          0:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_RD_DISABLED                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_RD_ENABLED                                  0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_WR                                          1:1 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_WR_DISABLED                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_WR_ENABLED                                  0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_GATOM                                       2:2 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_GATOM_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_GATOM_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_GRED                                        3:3 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_GRED_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_GRED_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CACHE_MGMT                                  4:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_DISABLED                         0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_ENABLED                          0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PREFETCH                                    5:5 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PREFETCH_DISABLED                           0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PREFETCH_ENABLED                            0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH                                6:6 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_DISABLED                       0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_ENABLED                        0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_MEMBAR                                      7:7 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_MEMBAR_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_MEMBAR_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_RD                                     8:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_RD_DISABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_RD_ENABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_WR                                     9:9 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_WR_DISABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_WR_ENABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_GRED                                 10:10 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_GRED_DISABLED                          0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_GRED_ENABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_GATOM                                11:11 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_DISABLED                         0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_ENABLED                          0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PACK_RD                                   12:12 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PACK_RD_DISABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PACK_RD_ENABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_WR                                 13:13 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_WR_DISABLED                          0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_WR_ENABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_GRED                               14:14 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_DISABLED                        0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_ENABLED                         0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM                              15:15 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_DISABLED                       0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_ENABLED                        0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_MULTICAST                                 16:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_MULTICAST_DISABLED                          0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_MULTICAST_ENABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_RDMC                                      17:17 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_RDMC_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_RDMC_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR                         18:18 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR_DISABLED                  0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR_ENABLED                   0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED                       19:19 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED_DISABLED                0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED_ENABLED                 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM                      20:20 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM_DISABLED               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM_ENABLED                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS                               22:22 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_DISABLED                        0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_ENABLED                         0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS                              23:23 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_DISABLED                       0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_ENABLED                        0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_VIDMEM                                    24:24 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_VIDMEM_ENABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_VIDMEM_DISABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PEER                                      25:25 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PEER_ENABLED                                0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PEER_DISABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_SYSMEM_C                                  26:26 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_SYSMEM_C_ENABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_SYSMEM_C_DISABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_SYSMEM_NC                                 27:27 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_ENABLED                           0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_DISABLED                          0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_TYPE                                      30:30 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_TYPE_VIRTUAL                                0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_TYPE_PHYSICAL                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_EXCLUSIVE                                 31:31 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_FALSE                             0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_TRUE                              0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK                 0x0000a0dc /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0                                        0x0000a0d4 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0__PRIV_LEVEL_MASK                       0x0000a0d8 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE                                  2:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_32MB                             0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_64MB                             0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_128MB                            0x2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_256MB                            0x3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_512MB                            0x4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_1024MB                           0x5 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_INIT                             0x3 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID                           31:16 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID_INIT                     0x0400 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_SRIOV_VMMU_TABLE(i)                      (0x0000a160+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU0_PRI_MMU_SRIOV_VMMU_TABLE__SIZE_1                                 32 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SRIOV_VMMU_TABLE__PRIV_LEVEL_MASK                0x0000a0d8 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP                                31:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP_INIT                     0x00000000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID(i)              (0x0000a218+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU0_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID__SIZE_1                         32 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID__PRIV_LEVEL_MASK        0x0000a0d8 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID_BITMAP                        31:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID_BITMAP_INIT             0xffffffff /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK                              0x0000a3fc /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION                     3:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL  0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED  0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0              0:0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1              1:1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2              2:2 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3              3:3 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION                    7:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0              0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1              0xc /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0             4:4 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1             5:5 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2             6:6 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3             7:7 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION                      8:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR         0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON           0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION                     9:9 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR        0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON          0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL               10:10 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED         0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED         0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL              11:11 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED        0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED        0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE                     31:12 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL                           0x0000a3f8 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK          0x0000a3fc /*       */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR             4:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK        0x1 /* RW--T */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT        0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP        0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR           5:5 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK      0x1 /* RW--T */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT      0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP      0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS                            0x0000a3f4 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA       0:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA     1:1 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA       2:2 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA     3:3 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_SA_DATA      4:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_SA_DATA    5:5 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_FA_DATA      6:6 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_FA_DATA    7:7 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_SA_DATA      8:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_SA_DATA    9:9 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_FA_DATA    10:10 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_FA_DATA  11:11 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_SA_DATA    12:12 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_SA_DATA  13:13 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_FA_DATA    14:14 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_FA_DATA  15:15 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET                           30:30 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_CLEAR                       0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_TASK                        0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_INIT                        0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT               0x0000a3f0 /* R--4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL               15:0 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT        0x0000 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE             31:16 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT             0x0000a3ec /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL             15:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT      0x0000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE           31:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS                           0x0000a3e8 /* R--4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_INDEX                           31:0 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_CACHELINE                       15:0 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_ERROR_MASK                     27:16 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID                         31:28 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA             0x0 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA             0x1 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB0_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB0_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB1_SA_DATA            0x2 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB1_FA_DATA            0x3 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB2_SA_DATA            0x4 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB2_FA_DATA            0x5 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB3_SA_DATA            0x6 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB3_FA_DATA            0x7 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL                           0x0000a3e4 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK          0x0000a3fc /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR             4:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK        0x1 /* RW--T */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT        0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP        0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR           5:5 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK      0x1 /* RW--T */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT      0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP      0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CONTROL                          0x0000a2b4 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CONTROL__PRIV_LEVEL_MASK         0x0000a3fc /*       */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR            4:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK       0x1 /* RW--T */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT       0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP       0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR          5:5 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK     0x1 /* RW--T */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT     0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP     0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS                           0x0000a2b8 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET                          30:30 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET_CLEAR                      0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET_TASK                       0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET_INIT                       0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT              0x0000a2bc /* R--4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_TOTAL              15:0 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_UNIQUE            31:16 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT      0x0000 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT            0x0000a2c0 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_TOTAL            15:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_UNIQUE          31:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT    0x0000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS                          0x0000a2c4 /* R--4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_INDEX                          31:0 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_CACHELINE                      15:0 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_ERROR_MASK                    27:16 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_RAM_ID                        31:28 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CONTROL                          0x0000a2c8 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CONTROL__PRIV_LEVEL_MASK         0x0000a3fc /*       */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR            4:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK       0x1 /* RW--T */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT       0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP       0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR          5:5 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK     0x1 /* RW--T */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT     0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP     0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS                           0x0000a2cc /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET                          30:30 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET_CLEAR                      0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET_TASK                       0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET_INIT                       0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT              0x0000a2d0 /* R--4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_TOTAL              15:0 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_UNIQUE            31:16 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT      0x0000 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT            0x0000a2d4 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_TOTAL            15:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_UNIQUE          31:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT    0x0000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS                          0x0000a2d8 /* R--4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_INDEX                          31:0 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_CACHELINE                      15:0 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_ERROR_MASK                    27:16 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_RAM_ID                        31:28 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CONTROL                          0x0000a2dc /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CONTROL__PRIV_LEVEL_MASK         0x0000a3fc /*       */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR            4:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK       0x1 /* RW--T */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT       0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP       0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR          5:5 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK     0x1 /* RW--T */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT     0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP     0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS                           0x0000a2e0 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET                          30:30 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET_CLEAR                      0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET_TASK                       0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET_INIT                       0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT              0x0000a2e4 /* R--4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_TOTAL              15:0 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_UNIQUE            31:16 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT      0x0000 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT            0x0000a2e8 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_TOTAL            15:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_UNIQUE          31:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT    0x0000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS                          0x0000a2ec /* R--4R */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_INDEX                          31:0 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_CACHELINE                      15:0 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_ERROR_MASK                    27:16 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_RAM_ID                        31:28 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS                            0x0000a3e0 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA       0:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA     1:1 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA       2:2 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA     3:3 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET                           30:30 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_CLEAR                       0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_TASK                        0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_INIT                        0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT               0x0000a3dc /* R--4R */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL               15:0 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT        0x0000 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE             31:16 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT             0x0000a3d8 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL             15:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT      0x0000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE           31:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS                           0x0000a3d4 /* R--4R */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_INDEX                           31:0 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_CACHELINE                       11:0 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_ERROR_MASK                     27:12 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID                         31:28 /* R-XVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA             0x0 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA             0x1 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUBMMU_GLOBAL_ESR                              0x0000a3d0 /* R--4R */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR                   0:0 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_NOT_PENDING       0x0 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_PENDING           0x1 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR                 1:1 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_NOT_PENDING     0x0 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_PENDING         0x1 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_ERROR_CONTAINMENT_CONTROL                        0x0000a3c0 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_ERROR_CONTAINMENT_CONTROL__PRIV_LEVEL_MASK       0x0000a3fc /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_REISSUE                 0:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_REISSUE_ENABLE          0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_REISSUE_DISABLE         0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_BLACKLIST               1:1 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_BLACKLIST_ENABLE        0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_BLACKLIST_DISABLE       0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER(i)        (0x0000a0e0+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1                    8 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__PRIV_LEVEL_MASK  0x0000a0dc /*       */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL                     31:0 /* RWEUF */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_INIT          0x00000000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_INVALID       0x00000000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB0        0x00000001 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB1        0x00000002 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB2        0x00000004 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB3        0x00000008 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB4        0x00000010 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB5        0x00000020 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB6        0x00000040 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB7        0x00000080 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB8        0x00000100 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB9        0x00000200 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB10       0x00000400 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB11       0x00000800 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB12       0x00001000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB13       0x00002000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB14       0x00004000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB15       0x00008000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_ALL_HSHUBS    0x0000001f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_PCIE          0x00000001 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_565MODE       0x80000000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_464MODE       0x40000000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG                      0x0000a100 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG__PRIV_LEVEL_MASK     0x0000a0dc /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS                        31:0 /* RWEUF */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INVALID          0x00000000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB0      0x00000001 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB1      0x00000002 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB2      0x00000004 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB3      0x00000008 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB4      0x00000010 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB5      0x00000020 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB6      0x00000040 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB7      0x00000080 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB8      0x00000100 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB9      0x00000200 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB10     0x00000400 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB11     0x00000800 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB12     0x00001000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB13     0x00002000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB14     0x00004000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB15     0x00008000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_BOTH_HSHUBS      0x00000003 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ALL_HSHUBS       0x0000001f /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_PCIE             0x00000001 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INIT             0x00000001 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK                        0x0000a108 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION               3:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0        0:0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1        1:1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2        2:2 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3        3:3 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION              7:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "gin_intr_ctrl" /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0        0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1        0xc /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0       4:4 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1       5:5 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2       6:6 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3       7:7 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION                8:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR   0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON     0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION               9:9 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR  0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON    0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL         10:10 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED   0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED   0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL        11:11 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED  0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED  0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE               31:12 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_gin_intr_ctrl_wr_secure" /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL         0xfffff /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE        0x00000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL                                        0x0000a10c /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL__PRIV_LEVEL_MASK                       0x0000a108 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_MESSAGE                                      31:0 /* RWEUF */
#define NV_PFB_HSMMU0_PRI_MMU_INTR_CTRL_MESSAGE_0_INIT                         0xc0000080 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT                                0x0000a110 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_NUM_RANGE_CHECKER              0x00000008 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE                                  3:0 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE_INIT                             0x2 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE                        29:29 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_CLEAR                    0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_SET                      0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_MODE                                30:30 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_ACCESS                           0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_DIRTY                            0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE                              31:31 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_FALSE                          0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_TRUE                           0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_INIT                           0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO(i)       (0x0000a114+(i)*8) /* RW-4A */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO__SIZE_1                   8 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_GRANULARITY             3:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_GRANULARITY_INIT        0x5 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL                   31:24 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL_INIT               0x00 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI(i)       (0x0000a118+(i)*8) /* RW-4A */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI__SIZE_1                   8 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL                    31:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL_INIT         0x00000000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL                                     0x0000a158 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL__PRIV_LEVEL_MASK                    0x0000a0d8 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE                     2:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_L2                  0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC              0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_RMW                 0x2 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_POWER               0x3 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_PCIE                0x4 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA                      4:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA_OFF                  0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA_ON                   0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE            5:5 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_L2         0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_FOLLOW_SYS_COH 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32                       8:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32_DISABLED              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32_ENABLED               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64                       9:9 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64_DISABLED              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64_ENABLED               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32                          10:10 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32_DISABLED                   0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32_ENABLED                    0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64                          11:11 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64_DISABLED                   0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64_ENABLED                    0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32              12:12 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32_DISABLED       0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32_ENABLED        0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64              13:13 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64_DISABLED       0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64_ENABLED        0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS                                  0x0000a15c /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS__PRIV_LEVEL_MASK                 0x0000a0dc /*       */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_V                                       6:0 /* R--VF */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_COUNT                                   6:0 /* R--VF */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE                             13:8 /* R--VF */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_ZERO                        0x00 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_TWO                         0x02 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_FOUR                        0x04 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_EIGHT                       0x08 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK                            23:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_INIT                        0x00 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER(i)        ((i)+16):((i)+16) /*       */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER__SIZE_1                   8 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_ENABLED                 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_DISABLED                0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_INIT                    0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2                24:24 /* R-EVF */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT             0x0 /* R-E-V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_ENABLED          0x1 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_DISABLED         0x0 /* R---V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM                            25:25 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_INIT                         0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_ENABLED                      0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_DISABLED                     0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE                          26:26 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_INIT                       0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_PEER                       0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_SYSMEM                     0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK                      27:27 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK_INIT                   0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK_ENABLED                0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK_DISABLED               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_NUM_ACTIVE_LTCS_SLICES_PER_LTC                        30:28 /* R--VF */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK       0x0000a2f0 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK(i)       (0x0000a2f4+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK__SIZE_1                  32 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK__PRIV_LEVEL_MASK 0x0000a2f0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK_BITMAP                 31:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK_BITMAP_INIT      0xffffffff /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK                   0x0000a2a8 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION          3:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0   0:0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1   1:1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2   2:2 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3   3:3 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION         7:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0   0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1   0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0  4:4 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1  5:5 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2  6:6 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3  7:7 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION           8:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION          9:9 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL    10:10 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL   11:11 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE          31:12 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK                     0x0000a2ac /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0     0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1     0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CC_GFID_TEE_STATE_ENABLE(i)              (0x0000a298+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU0_PRI_MMU_CC_GFID_TEE_STATE_ENABLE__SIZE_1                          2 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CC_GFID_TEE_STATE_ENABLE__PRIV_LEVEL_MASK        0x0000a2a8 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CC_GFID_TEE_STATE_ENABLE_BITMASK                       31:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_CC_GFID_TEE_STATE_ENABLE_BITMASK_INIT            0x00000000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE(i)                          (0x0000a2a0+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE__SIZE_1                                      2 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE__PRIV_LEVEL_MASK                    0x0000a2ac /*       */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_BITMASK                                   31:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_GFID_DISABLE_BITMASK_INIT                        0x00000000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK                    0x0000a3bc /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION           3:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0    0:0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1    1:1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2    2:2 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3    3:3 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION          7:4 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0   4:4 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1   5:5 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2   6:6 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3   7:7 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION            8:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION           9:9 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL     10:10 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL    11:11 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_ENABLE           31:12 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOTTOM                             0x0000a3b8 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOTTOM__PRIV_LEVEL_MASK            0x0000a3bc /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOTTOM_PER_SLICE                         19:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOTTOM_PER_SLICE_INIT                 0x00000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_MIDDLE                             0x0000a3b4 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_MIDDLE__PRIV_LEVEL_MASK            0x0000a3bc /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE                         19:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_INIT                 0x00000 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE            0x01000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE_LG2        0x0000c /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0                      0x0000a3b0 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0__PRIV_LEVEL_MASK     0x0000a3bc /*       */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL                        10:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_INIT                  0x603 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_0                0x603 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_1                0x423 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_2                0x621 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_3                0x40b /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_4                0x429 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_5                0x4a1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_6                0x681 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_7                0x407 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_8                0x40d /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_9                0x419 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_10               0x431 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_11               0x461 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_12               0x4c1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_13               0x581 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_14               0x701 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CG                                               0x0000a0b0 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_DLY_CNT                                      5:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_DLY_CNT_HWINIT                              0x02 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_DLY_CNT__PROD                               0x02 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_DLY_CNT__MIN_LIMIT                          0x02 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_EN                                           6:6 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_EN_ENABLED                                   0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_EN_DISABLED                                  0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_EN__PROD                                     0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CG_STATE_CG_EN                                          7:7 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_STATE_CG_EN_ENABLED                                  0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_STATE_CG_EN_DISABLED                                 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_STATE_CG_EN__PROD                                    0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_STALL_CG_DLY_CNT                                    13:8 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_STALL_CG_DLY_CNT_HWINIT                             0x02 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_STALL_CG_DLY_CNT__PROD                              0x02 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_STALL_CG_EN                                        14:14 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_CG_STALL_CG_EN_ENABLED                                  0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CG_STALL_CG_EN_DISABLED                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CG_STALL_CG_EN__PROD                                    0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CG_QUIESCENT_CG_EN                                    15:15 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_QUIESCENT_CG_EN_ENABLED                              0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_QUIESCENT_CG_EN_DISABLED                             0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_QUIESCENT_CG_EN__PROD                                0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_WAKEUP_DLY_CNT                                     19:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_CG_WAKEUP_DLY_CNT_HWINIT                                0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CG_WAKEUP_DLY_CNT__PROD                                 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CG_WAKEUP_DLY_CNT__MIN_LIMIT                            0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_CNT                                      23:20 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_CNT_FULLSPEED                              0xf /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_CNT__PROD                                  0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_DI_DT_SKEW_VAL                                     27:24 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_DI_DT_SKEW_VAL_HWINIT                                0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_DI_DT_SKEW_VAL__PROD                                 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_EN                                       28:28 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_EN_ENABLED                                 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_EN_DISABLED                                0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_EN__PROD                                   0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_SW_OVER                                  29:29 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_SW_OVER_EN                                 0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_SW_OVER_DIS                                0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_SW_OVER__PROD                              0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_PAUSE_CG_EN                                        30:30 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_PAUSE_CG_EN_ENABLED                                  0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_PAUSE_CG_EN_DISABLED                                 0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_PAUSE_CG_EN__PROD                                    0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_HALT_CG_EN                                         31:31 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_HALT_CG_EN_ENABLED                                   0x1 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_HALT_CG_EN_DISABLED                                  0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG_HALT_CG_EN__PROD                                     0x0 /*       */
#define NV_PFB_HSMMU0_PRI_MMU_CG1                                              0x0000a0b4 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_CG1_MONITOR_CG_EN                                       0:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_CG1_MONITOR_CG_EN_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CG1_MONITOR_CG_EN_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CG1_MONITOR_CG_EN__PROD                                 0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CG1_SLCG                                               11:1 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_CG1_SLCG_ENABLED                                      0x000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_CG1_SLCG_DISABLED                                     0x7ff /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_CG1_SLCG__PROD                                        0x000 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PG                                               0x0000a0b8 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_BLPG_DLY_CNT                                    7:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_BLPG_DLY_CNT_HWINIT                            0x0a /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_ELPG_EN_OFFSET_CNT                                  15:8 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PG_ELPG_EN_OFFSET_CNT_HWINIT                           0x0a /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_BLPG_EN                                       16:16 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_BLPG_EN_ENABLED                                 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_BLPG_EN_DISABLED                                0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_DIS_EARLY_WUP                                      17:17 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PG_DIS_EARLY_WUP_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_DIS_EARLY_WUP_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_DEEP_ELPG_EN                                       18:18 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PG_DEEP_ELPG_EN_ENABLED                                 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_DEEP_ELPG_EN_DISABLED                                0x0 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_ELPG_EN                                       19:19 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_ELPG_EN_ENABLED                                 0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_ELPG_EN_DISABLED                                0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_DIDT_DELAY                                         23:20 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PG_DIDT_DELAY_HWINIT                                    0xa /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_RESET_DURATION                                     26:24 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PG_RESET_DURATION_HWINIT                                0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_CLAMP_DELAY                                        29:27 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PG_CLAMP_DELAY_HWINIT                                   0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_ZONE_OFF_MASK                                      30:30 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PG_ZONE_OFF_MASK_HWINIT                                 0x1 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_SOFT_GATING_EN                                     31:31 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PG_SOFT_GATING_EN_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU0_PRI_MMU_PG_SOFT_GATING_EN_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PG1                                              0x0000a0c0 /* RW-4R */
#define NV_PFB_HSMMU0_PRI_MMU_PG1_ZONE_SEQ                                           23:0 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PG1_ZONE_SEQ_HWINIT                                0x053977 /* RWE-V */
#define NV_PFB_HSMMU0_PRI_MMU_PG1_ZONE_MASK                                         31:24 /* RWEVF */
#define NV_PFB_HSMMU0_PRI_MMU_PG1_ZONE_MASK_HWINIT                                   0xff /* RWE-V */
#define NV_PFB_HSMMU1                                               0x0000a7ff:0x0000a400 /* RW--D */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_ATOM_SIZE                                4096
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_ATOM_SIZE_LG2                             0xC
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_0                           0x603
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_1                           0x623
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_2                           0x623
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_3                           0x62B
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_4                           0x62B
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_5                           0x6A3
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_6                           0x6A3
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_7                           0x62F
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_8                           0x62F
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_9                           0x63B
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_10                          0x63B
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_11                          0x6E3
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_12                          0x6E3
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_13                          0x7A3
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_SWIZID_MASK_14                          0x7A3
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK                             0x0000a4d8 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION                    3:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0             0:0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1             1:1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2             2:2 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3             3:3 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION                   7:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0            4:4 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1            5:5 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2            6:6 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3            7:7 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION                     8:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR        0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON          0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION                    9:9 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR       0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON         0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL              10:10 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED        0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED        0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL             11:11 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED       0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED       0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_ENABLE                    31:12 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL                                             0x0000a480 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL__PRIV_LEVEL_MASK                            0x0000a4d8 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_VM_PG_SIZE                                         0:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_VM_PG_SIZE_128KB                                   0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_VM_PG_SIZE_64KB                                    0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_COMP_FAULT                                         2:2 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_COMP_FAULT_ENABLED                                 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_COMP_FAULT_DISABLED                                0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_MISS_GRAN                                          4:3 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_MISS_GRAN_FULL                                     0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_MISS_GRAN_HALF                                     0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_MISS_GRAN_QUARTER                                  0x2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_MISS_GRAN_NO_PTE_COMP                              0x3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_CACHE_MODE                                         6:5 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_CACHE_MODE_ON                                      0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS                     0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS                      0x2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_CACHE_MODE_OFF                                     0x3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_L2_SEND_MODE                                       9:9 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_L2_SEND_MODE_ONE_PTE                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_L2_SEND_MODE_WHOLE_CL                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE                           25:24 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_L2                          0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC                      0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_RMW                         0x2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_POWER                       0x3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA                            26:26 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_OFF                          0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_ON                           0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_CACHE_MODE_PHYS                                  29:28 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_CACHE_MODE_PHYS_ON                                 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_CACHE_MODE_PHYS_EVICT_SMPG_PARTIALS                0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_CACHE_MODE_PHYS_EVICT_ALL_PARTIALS                 0x2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CTRL_CACHE_MODE_PHYS_OFF                                0x3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL                                         0x0000a4a0 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_UTLB_SIZE                                      1:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_UTLB_SIZE_INIT                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_UTLB_RB_SIZE                                   3:2 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_UTLB_RB_SIZE_INIT                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_NVL_L1TLB_SIZE                                 5:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_NVL_L1TLB_SIZE_INIT                            0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_NVL_L1TLB_FA_SIZE                              7:6 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_NVL_L1TLB_FA_SIZE_INIT                         0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_NVL_L1TLB_RB_SIZE                              9:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_NVL_L1TLB_RB_SIZE_INIT                         0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_BIG_PG                   11:10 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_BIG_PG_INIT                0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_SMALL_PG                 13:12 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_SMALL_PG_INIT              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_NVL_UTLB_SIZE                                15:14 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_NVL_UTLB_SIZE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_L1TLB_SIZE                                   17:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_L1TLB_SIZE_INIT                                0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_L1TLB_FA_SIZE                                19:18 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_L1TLB_FA_SIZE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_L1TLB_RB_SIZE                                21:20 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_L1TLB_RB_SIZE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_BIG_PG                       23:22 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_BIG_PG_INIT                    0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_SMALL_PG                     25:24 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_SMALL_PG_INIT                  0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE                      26:26 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE_FALSE                  0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE_TRUE                   0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE                       27:27 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE_FALSE                   0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE_TRUE                    0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_NVL_UTLB_RB_SIZE                             29:28 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_NVL_UTLB_RB_SIZE_INIT                          0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_SECURE_LOCK                                  30:30 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_SECURE_LOCK_FALSE                              0x0 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_SECURE_LOCK_INIT                               0x0 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_SECURE_LOCK_TRUE                               0x1 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE                    31:31 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE_TRUE                 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE_FALSE                0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_MISC                                         0x0000a4a8 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_MISC_UTLB_UF                                        2:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_MISC_UTLB_UF_INIT                                   0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_MISC_L1TLB_UF                                       5:3 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_MISC_L1TLB_UF_INIT                                  0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_MISC_NVL_UTLB_UF                                    8:6 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_MISC_NVL_UTLB_UF_INIT                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_MISC_NVL_L1TLB_UF                                  11:9 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_TLB_MISC_NVL_L1TLB_UF_INIT                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CAPABILITIES                                     0x0000a4ac /* R--4R */
#define NV_PFB_HSMMU1_PRI_MMU_CAPABILITIES_CE                                         0:0 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_CAPABILITIES_CE_YES                                     0x1 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_CAPABILITIES_CE_NO                                      0x0 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_CAPABILITIES_NVLINK                                     1:1 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_CAPABILITIES_NVLINK_YES                                 0x1 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_CAPABILITIES_NVLINK_NO                                  0x0 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_CAPABILITIES_CHI                                        2:2 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_CAPABILITIES_CHI_YES                                    0x1 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_CAPABILITIES_CHI_NO                                     0x0 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_CAPABILITIES_PCIE                                       3:3 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_CAPABILITIES_PCIE_YES                                   0x1 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_CAPABILITIES_PCIE_NO                                    0x0 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH                                         0x0000a4a4 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_DISABLE                                  0:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_DISABLE_FALSE                            0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_DISABLE_TRUE                             0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_BIG_DISABLE                                    1:1 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_BIG_DISABLE_FALSE                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_BIG_DISABLE_TRUE                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_UNFILLED_DISABLE                               2:2 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_UNFILLED_DISABLE_FALSE                         0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_UNFILLED_DISABLE_TRUE                          0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_ENABLE                                         3:3 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_ENABLE_TRUE                                    0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_INCR_ONLY                                      4:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_INCR_ONLY_FALSE                                0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_INCR_ONLY_TRUE                                 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL                             5:5 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL_FALSE                       0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL_TRUE                        0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_ATSGPA_DISABLE                                 6:6 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_ATSGPA_DISABLE_FALSE                           0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_ATSGPA_DISABLE_TRUE                            0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE                               7:7 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE_FALSE                         0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE_TRUE                          0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH                           12:12 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_DISABLE                     0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_ENABLE                      0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE                         15:13 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_1                         0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_2                         0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_4                         0x2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_8                         0x3 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_16                        0x4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_32                        0x5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_64                        0x6 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE                            16:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE_FALSE                        0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE_TRUE                         0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_BIG_DISABLE                              17:17 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_BIG_DISABLE_FALSE                          0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_BIG_DISABLE_TRUE                           0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE                         18:18 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE_FALSE                     0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE_TRUE                      0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_ENABLE                                   19:19 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_ENABLE_TRUE                                0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_INCR_ONLY                                20:20 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_INCR_ONLY_FALSE                            0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_INCR_ONLY_TRUE                             0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_PREF_ON_FILL                       21:21 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_PREF_ON_FILL_FALSE                   0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_PREF_ON_FILL_TRUE                    0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_ATSGPA_DISABLE                           22:22 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_ATSGPA_DISABLE_FALSE                       0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_ATSGPA_DISABLE_TRUE                        0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SRIOVGPA_DISABLE                         23:23 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SRIOVGPA_DISABLE_FALSE                     0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SRIOVGPA_DISABLE_TRUE                      0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH                       28:28 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH_DISABLE                 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH_ENABLE                  0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE                     31:29 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_1                     0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_2                     0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_4                     0x2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_8                     0x3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_16                    0x4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_32                    0x5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_64                    0x6 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_CTRL                                       0x0000a4c4 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_CTRL_WR_KIND                                      7:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_CTRL_WR_KIND_INIT                                0x00 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_CTRL_RD_KIND                                     15:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_CTRL_RD_KIND_INIT                                0x00 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_CTRL_DEBUG                                      16:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_CTRL_DEBUG_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_CTRL_DEBUG_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_CTRL_PAGE_SIZE                                  18:17 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_4KB                                0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_64KB                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_128KB                              0x2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_1MB                                0x3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_WR                                         0x0000a4c8 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_WR_APERTURE                                       1:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_WR_APERTURE_PEER_MEM                              0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_C                             0x2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_NC                            0x3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_WR_VOL                                            2:2 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_WR_VOL_FALSE                                      0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_WR_VOL_TRUE                                       0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_WR_ADDR                                          31:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_WR_ADDR_INIT                                0x0000000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT                           0x000000c /*       */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_RD                                         0x0000a4cc /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_RD_APERTURE                                       1:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_RD_APERTURE_PEER_MEM                              0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_C                             0x2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_NC                            0x3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_RD_VOL                                            2:2 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_RD_VOL_FALSE                                      0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_RD_VOL_TRUE                                       0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_RD_ADDR                                          31:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_RD_ADDR_INIT                                0x0000000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT                           0x000000c /*       */
#define NV_PFB_HSMMU1_PRI_MMU_PM                                               0x0000a484 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT                                               7:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_00                                       0x00 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_01                                       0x01 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_02                                       0x02 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_03                                       0x03 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_04                                       0x04 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_05                                       0x05 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_06                                       0x06 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_07                                       0x07 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_08                                       0x08 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_09                                       0x09 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_0A                                       0x0a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_0B                                       0x0b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_0C                                       0x0c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_0D                                       0x0d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_0E                                       0x0e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_0F                                       0x0f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_10                                       0x10 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_11                                       0x11 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_12                                       0x12 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_13                                       0x13 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_14                                       0x14 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_15                                       0x15 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_16                                       0x16 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_17                                       0x17 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_18                                       0x18 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_19                                       0x19 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_1A                                       0x1a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_1B                                       0x1b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_1C                                       0x1c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_1D                                       0x1d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_1E                                       0x1e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_1F                                       0x1f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_20                                       0x20 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_21                                       0x21 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_22                                       0x22 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_23                                       0x23 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_24                                       0x24 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_25                                       0x25 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_26                                       0x26 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_27                                       0x27 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_28                                       0x28 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_29                                       0x29 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_2A                                       0x2a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_2B                                       0x2b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_2C                                       0x2c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_2D                                       0x2d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_2E                                       0x2e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_2F                                       0x2f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_30                                       0x30 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_31                                       0x31 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_32                                       0x32 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_33                                       0x33 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_34                                       0x34 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_35                                       0x35 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_36                                       0x36 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_37                                       0x37 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_38                                       0x38 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_39                                       0x39 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_3A                                       0x3a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_3B                                       0x3b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_3C                                       0x3c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_3D                                       0x3d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_3E                                       0x3e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_3F                                       0x3f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_40                                       0x40 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_41                                       0x41 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_42                                       0x42 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_43                                       0x43 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_44                                       0x44 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_45                                       0x45 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_46                                       0x46 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_47                                       0x47 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_48                                       0x48 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_49                                       0x49 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_4A                                       0x4a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_4B                                       0x4b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_4C                                       0x4c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_4D                                       0x4d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_4E                                       0x4e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_4F                                       0x4f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_50                                       0x50 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_51                                       0x51 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_52                                       0x52 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_53                                       0x53 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_54                                       0x54 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_55                                       0x55 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_56                                       0x56 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_57                                       0x57 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_58                                       0x58 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_59                                       0x59 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_5A                                       0x5a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_5B                                       0x5b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_5C                                       0x5c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_5D                                       0x5d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_5E                                       0x5e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_5F                                       0x5f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_60                                       0x60 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_61                                       0x61 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_62                                       0x62 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_63                                       0x63 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_64                                       0x64 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_65                                       0x65 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_66                                       0x66 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_67                                       0x67 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_68                                       0x68 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_69                                       0x69 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_6A                                       0x6a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_6B                                       0x6b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_6C                                       0x6c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_6D                                       0x6d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_6E                                       0x6e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_6F                                       0x6f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_70                                       0x70 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_71                                       0x71 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_72                                       0x72 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_73                                       0x73 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_74                                       0x74 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_75                                       0x75 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_76                                       0x76 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_77                                       0x77 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_78                                       0x78 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_79                                       0x79 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_7A                                       0x7a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_7B                                       0x7b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_7C                                       0x7c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_7D                                       0x7d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_7E                                       0x7e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_7F                                       0x7f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_80                                       0x80 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_81                                       0x81 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_82                                       0x82 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_83                                       0x83 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_84                                       0x84 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_85                                       0x85 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_86                                       0x86 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_87                                       0x87 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_88                                       0x88 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_89                                       0x89 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_8A                                       0x8a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_8B                                       0x8b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_8C                                       0x8c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_8D                                       0x8d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_8E                                       0x8e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_8F                                       0x8f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_90                                       0x90 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_91                                       0x91 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_92                                       0x92 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_93                                       0x93 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_94                                       0x94 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_95                                       0x95 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_96                                       0x96 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_97                                       0x97 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_98                                       0x98 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_99                                       0x99 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_9A                                       0x9a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_9B                                       0x9b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_9C                                       0x9c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_9D                                       0x9d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_9E                                       0x9e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_9F                                       0x9f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_A0                                       0xa0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_A1                                       0xa1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_A2                                       0xa2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_A3                                       0xa3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_A4                                       0xa4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_A5                                       0xa5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_A6                                       0xa6 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_A7                                       0xa7 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_A8                                       0xa8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_A9                                       0xa9 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_AA                                       0xaa /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_AB                                       0xab /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_AC                                       0xac /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_AD                                       0xad /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_AE                                       0xae /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_AF                                       0xaf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_B0                                       0xb0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_B1                                       0xb1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_B2                                       0xb2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_B3                                       0xb3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_B4                                       0xb4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_B5                                       0xb5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_B6                                       0xb6 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_B7                                       0xb7 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_B8                                       0xb8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_B9                                       0xb9 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_BA                                       0xba /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_BB                                       0xbb /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_BC                                       0xbc /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_BD                                       0xbd /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_BE                                       0xbe /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_BF                                       0xbf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_C0                                       0xc0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_C1                                       0xc1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_C2                                       0xc2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_C3                                       0xc3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_C4                                       0xc4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_C5                                       0xc5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_C6                                       0xc6 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_C7                                       0xc7 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_C8                                       0xc8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_C9                                       0xc9 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_CA                                       0xca /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_CB                                       0xcb /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_CC                                       0xcc /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_CD                                       0xcd /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_CE                                       0xce /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_CF                                       0xcf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_D0                                       0xd0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_D1                                       0xd1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_D2                                       0xd2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_D3                                       0xd3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_D4                                       0xd4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_D5                                       0xd5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_D6                                       0xd6 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_D7                                       0xd7 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_D8                                       0xd8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_D9                                       0xd9 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_DA                                       0xda /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_DB                                       0xdb /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_DC                                       0xdc /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_DD                                       0xdd /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_DE                                       0xde /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_DF                                       0xdf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_E0                                       0xe0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_E1                                       0xe1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_E2                                       0xe2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_E3                                       0xe3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_E4                                       0xe4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_E5                                       0xe5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_E6                                       0xe6 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_E7                                       0xe7 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_E8                                       0xe8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_E9                                       0xe9 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_EA                                       0xea /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_EB                                       0xeb /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_EC                                       0xec /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_ED                                       0xed /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_EE                                       0xee /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_EF                                       0xef /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_F0                                       0xf0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_F1                                       0xf1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_F2                                       0xf2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_F3                                       0xf3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_F4                                       0xf4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_F5                                       0xf5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_F6                                       0xf6 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_F7                                       0xf7 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_F8                                       0xf8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_F9                                       0xf9 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_FA                                       0xfa /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_FB                                       0xfb /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_FC                                       0xfc /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_GRP_FD                                       0xfd /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_STATIC_PATTERN_5_4_GROUP                     0xfe /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_STATIC_PATTERN_A_4_GROUP                     0xff /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1                                         15:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_00                                  0x00 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_01                                  0x01 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_02                                  0x02 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_03                                  0x03 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_04                                  0x04 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_05                                  0x05 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_06                                  0x06 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_07                                  0x07 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_08                                  0x08 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_09                                  0x09 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_0A                                  0x0a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_0B                                  0x0b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_0C                                  0x0c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_0D                                  0x0d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_0E                                  0x0e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_0F                                  0x0f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_10                                  0x10 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_11                                  0x11 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_12                                  0x12 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_13                                  0x13 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_14                                  0x14 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_15                                  0x15 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_16                                  0x16 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_17                                  0x17 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_18                                  0x18 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_19                                  0x19 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_1A                                  0x1a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_1B                                  0x1b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_1C                                  0x1c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_1D                                  0x1d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_1E                                  0x1e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_1F                                  0x1f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_20                                  0x20 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_21                                  0x21 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_22                                  0x22 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_23                                  0x23 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_24                                  0x24 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_25                                  0x25 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_26                                  0x26 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_27                                  0x27 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_28                                  0x28 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_29                                  0x29 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_2A                                  0x2a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_2B                                  0x2b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_2C                                  0x2c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_2D                                  0x2d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_2E                                  0x2e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_2F                                  0x2f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_30                                  0x30 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_31                                  0x31 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_32                                  0x32 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_33                                  0x33 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_34                                  0x34 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_35                                  0x35 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_36                                  0x36 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_37                                  0x37 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_38                                  0x38 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_39                                  0x39 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_3A                                  0x3a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_3B                                  0x3b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_3C                                  0x3c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_3D                                  0x3d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_3E                                  0x3e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_3F                                  0x3f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_40                                  0x40 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_41                                  0x41 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_42                                  0x42 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_43                                  0x43 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_44                                  0x44 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_45                                  0x45 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_46                                  0x46 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_47                                  0x47 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_48                                  0x48 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_49                                  0x49 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_4A                                  0x4a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_4B                                  0x4b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_4C                                  0x4c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_4D                                  0x4d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_4E                                  0x4e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_4F                                  0x4f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_50                                  0x50 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_51                                  0x51 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_52                                  0x52 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_53                                  0x53 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_54                                  0x54 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_55                                  0x55 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_56                                  0x56 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_57                                  0x57 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_58                                  0x58 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_59                                  0x59 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_5A                                  0x5a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_5B                                  0x5b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_5C                                  0x5c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_5D                                  0x5d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_5E                                  0x5e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_5F                                  0x5f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_60                                  0x60 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_61                                  0x61 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_62                                  0x62 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_63                                  0x63 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_64                                  0x64 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_65                                  0x65 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_66                                  0x66 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_67                                  0x67 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_68                                  0x68 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_69                                  0x69 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_6A                                  0x6a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_6B                                  0x6b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_6C                                  0x6c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_6D                                  0x6d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_6E                                  0x6e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_6F                                  0x6f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_70                                  0x70 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_71                                  0x71 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_72                                  0x72 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_73                                  0x73 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_74                                  0x74 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_75                                  0x75 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_76                                  0x76 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_77                                  0x77 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_78                                  0x78 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_79                                  0x79 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_7A                                  0x7a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_7B                                  0x7b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_7C                                  0x7c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_7D                                  0x7d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_7E                                  0x7e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_7F                                  0x7f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_80                                  0x80 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_81                                  0x81 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_82                                  0x82 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_83                                  0x83 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_84                                  0x84 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_85                                  0x85 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_86                                  0x86 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_87                                  0x87 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_88                                  0x88 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_89                                  0x89 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_8A                                  0x8a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_8B                                  0x8b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_8C                                  0x8c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_8D                                  0x8d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_8E                                  0x8e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_8F                                  0x8f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_90                                  0x90 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_91                                  0x91 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_92                                  0x92 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_93                                  0x93 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_94                                  0x94 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_95                                  0x95 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_96                                  0x96 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_97                                  0x97 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_98                                  0x98 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_99                                  0x99 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_9A                                  0x9a /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_9B                                  0x9b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_9C                                  0x9c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_9D                                  0x9d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_9E                                  0x9e /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_9F                                  0x9f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_A0                                  0xa0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_A1                                  0xa1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_A2                                  0xa2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_A3                                  0xa3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_A4                                  0xa4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_A5                                  0xa5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_A6                                  0xa6 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_A7                                  0xa7 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_A8                                  0xa8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_A9                                  0xa9 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_AA                                  0xaa /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_AB                                  0xab /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_AC                                  0xac /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_AD                                  0xad /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_AE                                  0xae /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_AF                                  0xaf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_B0                                  0xb0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_B1                                  0xb1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_B2                                  0xb2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_B3                                  0xb3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_B4                                  0xb4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_B5                                  0xb5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_B6                                  0xb6 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_B7                                  0xb7 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_B8                                  0xb8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_B9                                  0xb9 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_BA                                  0xba /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_BB                                  0xbb /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_BC                                  0xbc /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_BD                                  0xbd /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_BE                                  0xbe /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_BF                                  0xbf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_C0                                  0xc0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_C1                                  0xc1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_C2                                  0xc2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_C3                                  0xc3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_C4                                  0xc4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_C5                                  0xc5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_C6                                  0xc6 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_C7                                  0xc7 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_C8                                  0xc8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_C9                                  0xc9 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_CA                                  0xca /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_CB                                  0xcb /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_CC                                  0xcc /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_CD                                  0xcd /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_CE                                  0xce /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_CF                                  0xcf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_D0                                  0xd0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_D1                                  0xd1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_D2                                  0xd2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_D3                                  0xd3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_D4                                  0xd4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_D5                                  0xd5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_D6                                  0xd6 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_D7                                  0xd7 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_D8                                  0xd8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_D9                                  0xd9 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_DA                                  0xda /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_DB                                  0xdb /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_DC                                  0xdc /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_DD                                  0xdd /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_DE                                  0xde /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_DF                                  0xdf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_E0                                  0xe0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_E1                                  0xe1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_E2                                  0xe2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_E3                                  0xe3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_E4                                  0xe4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_E5                                  0xe5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_E6                                  0xe6 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_E7                                  0xe7 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_E8                                  0xe8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_E9                                  0xe9 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_EA                                  0xea /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_EB                                  0xeb /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_EC                                  0xec /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_ED                                  0xed /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_EE                                  0xee /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_EF                                  0xef /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_F0                                  0xf0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_F1                                  0xf1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_F2                                  0xf2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_F3                                  0xf3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_F4                                  0xf4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_F5                                  0xf5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_F6                                  0xf6 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_F7                                  0xf7 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_F8                                  0xf8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_F9                                  0xf9 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_FA                                  0xfa /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_FB                                  0xfb /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_FC                                  0xfc /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_GRP_FD                                  0xfd /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_5_4_GROUP                0xfe /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_A_4_GROUP                0xff /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_BLK_ACT                                            30:30 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_BLK_ACT_DISABLE                                      0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_BLK_ACT_ENABLE                                       0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_BLK_ACT_INIT                                         0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_ENABLE                                             31:31 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_ENABLE_DISABLE                                       0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_ENABLE_ENABLE                                        0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_ENABLE_INIT                                          0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_ADDR_LOW                                      0x0000a488 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_PM_ADDR_LOW_ALIGNMENT                            0x00000008 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_PM_ADDR_LOW_BITS                                       31:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_ADDR_LOW_BITS_INIT                            0x00000000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UPPER_ADDR_LOW                                0x0000a48c /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UPPER_ADDR_LOW_BITS                                 23:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UPPER_ADDR_LOW_BITS_INIT                        0x000000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_ADDR_HIGH                                     0x0000a490 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_PM_ADDR_HIGH_ALIGNMENT                           0x00000008 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_PM_ADDR_HIGH_BITS                                      31:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_ADDR_HIGH_BITS_INIT                           0x00000000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UPPER_ADDR_HIGH                               0x0000a494 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS                                23:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS_INIT                       0x000000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK                                     0x0000a498 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE0                                        0:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE0_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE0_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE1                                        1:1 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE1_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE1_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE2                                        2:2 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE2_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE2_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE3                                        3:3 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE3_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE3_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE4                                        4:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE4_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE4_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE5                                        5:5 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE5_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE5_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE6                                        6:6 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE6_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE6_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE7                                        7:7 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE7_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE7_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE8                                        8:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE8_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE8_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE9                                        9:9 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE9_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE9_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE10                                     10:10 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE10_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE10_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE11                                     11:11 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE11_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE11_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE12                                     12:12 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE12_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE12_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE13                                     13:13 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE13_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE13_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE14                                     14:14 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE14_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE14_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE15                                     15:15 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE15_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_CE15_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL0                                     16:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL0_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL0_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL1                                     17:17 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL1_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL1_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL2                                     18:18 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL2_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL2_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL3                                     19:19 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL3_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL3_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL4                                     20:20 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL4_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL4_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL5                                     21:21 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL5_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL5_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL6                                     22:22 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL6_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL6_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL7                                     23:23 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL7_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL7_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL8                                     24:24 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL8_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL8_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL9                                     25:25 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL9_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL9_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL10                                    26:26 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL10_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL10_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL11                                    27:27 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL11_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL11_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL12                                    28:28 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL12_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL12_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL13                                    29:29 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL13_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL13_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL14                                    30:30 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL14_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL14_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL15                                    31:31 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL15_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_UNIT_MASK_NVL15_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK                                      0x0000a49c /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_RD                                          0:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_RD_DISABLED                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_RD_ENABLED                                  0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_WR                                          1:1 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_WR_DISABLED                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_WR_ENABLED                                  0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_GATOM                                       2:2 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_GATOM_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_GATOM_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_GRED                                        3:3 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_GRED_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_GRED_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_CACHE_MGMT                                  4:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_DISABLED                         0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_ENABLED                          0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PREFETCH                                    5:5 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PREFETCH_DISABLED                           0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PREFETCH_ENABLED                            0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH                                6:6 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_DISABLED                       0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_ENABLED                        0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_MEMBAR                                      7:7 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_MEMBAR_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_MEMBAR_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PHYS_RD                                     8:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PHYS_RD_DISABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PHYS_RD_ENABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PHYS_WR                                     9:9 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PHYS_WR_DISABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PHYS_WR_ENABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PHYS_GRED                                 10:10 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PHYS_GRED_DISABLED                          0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PHYS_GRED_ENABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PHYS_GATOM                                11:11 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_DISABLED                         0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_ENABLED                          0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PACK_RD                                   12:12 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PACK_RD_DISABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PACK_RD_ENABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_CONCAT_WR                                 13:13 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_CONCAT_WR_DISABLED                          0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_CONCAT_WR_ENABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_CONCAT_GRED                               14:14 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_DISABLED                        0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_ENABLED                         0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM                              15:15 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_DISABLED                       0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_ENABLED                        0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_MULTICAST                                 16:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_MULTICAST_DISABLED                          0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_MULTICAST_ENABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_RDMC                                      17:17 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_RDMC_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_RDMC_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR                         18:18 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR_DISABLED                  0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR_ENABLED                   0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED                       19:19 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED_DISABLED                0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED_ENABLED                 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM                      20:20 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM_DISABLED               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM_ENABLED                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS                               22:22 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_DISABLED                        0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_ENABLED                         0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS                              23:23 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_DISABLED                       0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_ENABLED                        0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_VIDMEM                                    24:24 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_VIDMEM_ENABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_VIDMEM_DISABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PEER                                      25:25 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PEER_ENABLED                                0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_PEER_DISABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_SYSMEM_C                                  26:26 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_SYSMEM_C_ENABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_SYSMEM_C_DISABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_SYSMEM_NC                                 27:27 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_ENABLED                           0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_DISABLED                          0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_TYPE                                      30:30 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_TYPE_VIRTUAL                                0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_TYPE_PHYSICAL                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_EXCLUSIVE                                 31:31 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_FALSE                             0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_TRUE                              0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK                 0x0000a4dc /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_CFG0                                        0x0000a4d4 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_CFG0__PRIV_LEVEL_MASK                       0x0000a4d8 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE                                  2:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_32MB                             0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_64MB                             0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_128MB                            0x2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_256MB                            0x3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_512MB                            0x4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_1024MB                           0x5 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_INIT                             0x3 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID                           31:16 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID_INIT                     0x0400 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_SRIOV_VMMU_TABLE(i)                      (0x0000a560+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU1_PRI_MMU_SRIOV_VMMU_TABLE__SIZE_1                                 32 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SRIOV_VMMU_TABLE__PRIV_LEVEL_MASK                0x0000a4d8 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP                                31:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP_INIT                     0x00000000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID(i)              (0x0000a618+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU1_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID__SIZE_1                         32 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID__PRIV_LEVEL_MASK        0x0000a4d8 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID_BITMAP                        31:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID_BITMAP_INIT             0xffffffff /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK                              0x0000a7fc /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION                     3:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL  0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED  0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0              0:0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1              1:1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2              2:2 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3              3:3 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION                    7:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0              0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1              0xc /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0             4:4 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1             5:5 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2             6:6 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3             7:7 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION                      8:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR         0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON           0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION                     9:9 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR        0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON          0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL               10:10 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED         0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED         0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL              11:11 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED        0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED        0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE                     31:12 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CONTROL                           0x0000a7f8 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK          0x0000a7fc /*       */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR             4:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK        0x1 /* RW--T */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT        0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP        0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR           5:5 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK      0x1 /* RW--T */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT      0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP      0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS                            0x0000a7f4 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA       0:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA     1:1 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA       2:2 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA     3:3 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_SA_DATA      4:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_SA_DATA    5:5 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_FA_DATA      6:6 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_FA_DATA    7:7 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_SA_DATA      8:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_SA_DATA    9:9 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_FA_DATA    10:10 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_FA_DATA  11:11 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_SA_DATA    12:12 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_SA_DATA  13:13 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_FA_DATA    14:14 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_FA_DATA  15:15 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET                           30:30 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_CLEAR                       0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_TASK                        0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_INIT                        0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT               0x0000a7f0 /* R--4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL               15:0 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT        0x0000 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE             31:16 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT             0x0000a7ec /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL             15:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT      0x0000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE           31:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS                           0x0000a7e8 /* R--4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_INDEX                           31:0 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_CACHELINE                       15:0 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_ERROR_MASK                     27:16 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID                         31:28 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA             0x0 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA             0x1 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB0_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB0_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB1_SA_DATA            0x2 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB1_FA_DATA            0x3 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB2_SA_DATA            0x4 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB2_FA_DATA            0x5 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB3_SA_DATA            0x6 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB3_FA_DATA            0x7 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CONTROL                           0x0000a7e4 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK          0x0000a7fc /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR             4:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK        0x1 /* RW--T */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT        0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP        0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR           5:5 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK      0x1 /* RW--T */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT      0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP      0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CONTROL                          0x0000a6b4 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CONTROL__PRIV_LEVEL_MASK         0x0000a7fc /*       */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR            4:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK       0x1 /* RW--T */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT       0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP       0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR          5:5 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK     0x1 /* RW--T */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT     0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP     0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS                           0x0000a6b8 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET                          30:30 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET_CLEAR                      0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET_TASK                       0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET_INIT                       0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT              0x0000a6bc /* R--4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_TOTAL              15:0 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_UNIQUE            31:16 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT      0x0000 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT            0x0000a6c0 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_TOTAL            15:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_UNIQUE          31:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT    0x0000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS                          0x0000a6c4 /* R--4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_INDEX                          31:0 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_CACHELINE                      15:0 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_ERROR_MASK                    27:16 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_RAM_ID                        31:28 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CONTROL                          0x0000a6c8 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CONTROL__PRIV_LEVEL_MASK         0x0000a7fc /*       */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR            4:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK       0x1 /* RW--T */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT       0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP       0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR          5:5 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK     0x1 /* RW--T */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT     0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP     0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS                           0x0000a6cc /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET                          30:30 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET_CLEAR                      0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET_TASK                       0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET_INIT                       0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT              0x0000a6d0 /* R--4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_TOTAL              15:0 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_UNIQUE            31:16 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT      0x0000 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT            0x0000a6d4 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_TOTAL            15:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_UNIQUE          31:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT    0x0000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS                          0x0000a6d8 /* R--4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_INDEX                          31:0 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_CACHELINE                      15:0 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_ERROR_MASK                    27:16 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_RAM_ID                        31:28 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CONTROL                          0x0000a6dc /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CONTROL__PRIV_LEVEL_MASK         0x0000a7fc /*       */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR            4:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK       0x1 /* RW--T */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT       0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP       0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR          5:5 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK     0x1 /* RW--T */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT     0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP     0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS                           0x0000a6e0 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET                          30:30 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET_CLEAR                      0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET_TASK                       0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET_INIT                       0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT              0x0000a6e4 /* R--4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_TOTAL              15:0 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_UNIQUE            31:16 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT      0x0000 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT            0x0000a6e8 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_TOTAL            15:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_UNIQUE          31:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT    0x0000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS                          0x0000a6ec /* R--4R */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_INDEX                          31:0 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_CACHELINE                      15:0 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_ERROR_MASK                    27:16 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_RAM_ID                        31:28 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS                            0x0000a7e0 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA       0:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA     1:1 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA       2:2 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA     3:3 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET                           30:30 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_CLEAR                       0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_TASK                        0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_INIT                        0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT               0x0000a7dc /* R--4R */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL               15:0 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT        0x0000 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE             31:16 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT             0x0000a7d8 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL             15:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT      0x0000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE           31:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS                           0x0000a7d4 /* R--4R */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_INDEX                           31:0 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_CACHELINE                       11:0 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_ERROR_MASK                     27:12 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID                         31:28 /* R-XVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA             0x0 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA             0x1 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUBMMU_GLOBAL_ESR                              0x0000a7d0 /* R--4R */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR                   0:0 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_NOT_PENDING       0x0 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_PENDING           0x1 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR                 1:1 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_NOT_PENDING     0x0 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_PENDING         0x1 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_ERROR_CONTAINMENT_CONTROL                        0x0000a7c0 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_ERROR_CONTAINMENT_CONTROL__PRIV_LEVEL_MASK       0x0000a7fc /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_REISSUE                 0:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_REISSUE_ENABLE          0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_REISSUE_DISABLE         0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_BLACKLIST               1:1 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_BLACKLIST_ENABLE        0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_BLACKLIST_DISABLE       0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER(i)        (0x0000a4e0+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1                    8 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__PRIV_LEVEL_MASK  0x0000a4dc /*       */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL                     31:0 /* RWEUF */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_INIT          0x00000000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_INVALID       0x00000000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB0        0x00000001 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB1        0x00000002 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB2        0x00000004 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB3        0x00000008 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB4        0x00000010 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB5        0x00000020 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB6        0x00000040 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB7        0x00000080 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB8        0x00000100 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB9        0x00000200 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB10       0x00000400 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB11       0x00000800 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB12       0x00001000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB13       0x00002000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB14       0x00004000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB15       0x00008000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_ALL_HSHUBS    0x0000001f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_PCIE          0x00000001 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_565MODE       0x80000000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_464MODE       0x40000000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG                      0x0000a500 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG__PRIV_LEVEL_MASK     0x0000a4dc /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS                        31:0 /* RWEUF */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INVALID          0x00000000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB0      0x00000001 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB1      0x00000002 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB2      0x00000004 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB3      0x00000008 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB4      0x00000010 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB5      0x00000020 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB6      0x00000040 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB7      0x00000080 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB8      0x00000100 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB9      0x00000200 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB10     0x00000400 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB11     0x00000800 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB12     0x00001000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB13     0x00002000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB14     0x00004000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB15     0x00008000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_BOTH_HSHUBS      0x00000003 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ALL_HSHUBS       0x0000001f /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_PCIE             0x00000001 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INIT             0x00000001 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK                        0x0000a508 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION               3:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0        0:0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1        1:1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2        2:2 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3        3:3 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION              7:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "gin_intr_ctrl" /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0        0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1        0xc /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0       4:4 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1       5:5 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2       6:6 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3       7:7 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION                8:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR   0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON     0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION               9:9 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR  0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON    0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL         10:10 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED   0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED   0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL        11:11 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED  0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED  0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE               31:12 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_gin_intr_ctrl_wr_secure" /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL         0xfffff /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE        0x00000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL                                        0x0000a50c /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL__PRIV_LEVEL_MASK                       0x0000a508 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_MESSAGE                                      31:0 /* RWEUF */
#define NV_PFB_HSMMU1_PRI_MMU_INTR_CTRL_MESSAGE_0_INIT                         0xc0000080 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT                                0x0000a510 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_NUM_RANGE_CHECKER              0x00000008 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE                                  3:0 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE_INIT                             0x2 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE                        29:29 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_CLEAR                    0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_SET                      0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_MODE                                30:30 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_ACCESS                           0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_DIRTY                            0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE                              31:31 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_FALSE                          0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_TRUE                           0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_INIT                           0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO(i)       (0x0000a514+(i)*8) /* RW-4A */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO__SIZE_1                   8 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_GRANULARITY             3:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_GRANULARITY_INIT        0x5 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL                   31:24 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL_INIT               0x00 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI(i)       (0x0000a518+(i)*8) /* RW-4A */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI__SIZE_1                   8 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL                    31:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL_INIT         0x00000000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL                                     0x0000a558 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL__PRIV_LEVEL_MASK                    0x0000a4d8 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE                     2:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_L2                  0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC              0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_RMW                 0x2 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_POWER               0x3 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_PCIE                0x4 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA                      4:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA_OFF                  0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA_ON                   0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE            5:5 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_L2         0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_FOLLOW_SYS_COH 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32                       8:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32_DISABLED              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32_ENABLED               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64                       9:9 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64_DISABLED              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64_ENABLED               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32                          10:10 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32_DISABLED                   0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32_ENABLED                    0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64                          11:11 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64_DISABLED                   0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64_ENABLED                    0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32              12:12 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32_DISABLED       0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32_ENABLED        0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64              13:13 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64_DISABLED       0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64_ENABLED        0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS                                  0x0000a55c /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS__PRIV_LEVEL_MASK                 0x0000a4dc /*       */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_V                                       6:0 /* R--VF */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_COUNT                                   6:0 /* R--VF */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE                             13:8 /* R--VF */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_ZERO                        0x00 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_TWO                         0x02 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_FOUR                        0x04 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_EIGHT                       0x08 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK                            23:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_INIT                        0x00 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER(i)        ((i)+16):((i)+16) /*       */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER__SIZE_1                   8 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_ENABLED                 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_DISABLED                0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_INIT                    0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2                24:24 /* R-EVF */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT             0x0 /* R-E-V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_ENABLED          0x1 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_DISABLED         0x0 /* R---V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM                            25:25 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_INIT                         0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_ENABLED                      0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_DISABLED                     0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE                          26:26 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_INIT                       0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_PEER                       0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_SYSMEM                     0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK                      27:27 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK_INIT                   0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK_ENABLED                0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK_DISABLED               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_NUM_ACTIVE_LTCS_SLICES_PER_LTC                        30:28 /* R--VF */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK       0x0000a6f0 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK(i)       (0x0000a6f4+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK__SIZE_1                  32 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK__PRIV_LEVEL_MASK 0x0000a6f0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK_BITMAP                 31:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK_BITMAP_INIT      0xffffffff /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK                   0x0000a6a8 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION          3:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0   0:0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1   1:1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2   2:2 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3   3:3 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION         7:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0   0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1   0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0  4:4 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1  5:5 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2  6:6 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3  7:7 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION           8:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION          9:9 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL    10:10 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL   11:11 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE          31:12 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK                     0x0000a6ac /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0     0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1     0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CC_GFID_TEE_STATE_ENABLE(i)              (0x0000a698+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU1_PRI_MMU_CC_GFID_TEE_STATE_ENABLE__SIZE_1                          2 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CC_GFID_TEE_STATE_ENABLE__PRIV_LEVEL_MASK        0x0000a6a8 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CC_GFID_TEE_STATE_ENABLE_BITMASK                       31:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_CC_GFID_TEE_STATE_ENABLE_BITMASK_INIT            0x00000000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE(i)                          (0x0000a6a0+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE__SIZE_1                                      2 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE__PRIV_LEVEL_MASK                    0x0000a6ac /*       */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_BITMASK                                   31:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_GFID_DISABLE_BITMASK_INIT                        0x00000000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK                    0x0000a7bc /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION           3:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0    0:0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1    1:1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2    2:2 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3    3:3 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION          7:4 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0   4:4 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1   5:5 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2   6:6 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3   7:7 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION            8:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION           9:9 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL     10:10 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL    11:11 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_ENABLE           31:12 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOTTOM                             0x0000a7b8 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOTTOM__PRIV_LEVEL_MASK            0x0000a7bc /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOTTOM_PER_SLICE                         19:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOTTOM_PER_SLICE_INIT                 0x00000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_MIDDLE                             0x0000a7b4 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_MIDDLE__PRIV_LEVEL_MASK            0x0000a7bc /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE                         19:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_INIT                 0x00000 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE            0x01000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE_LG2        0x0000c /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0                      0x0000a7b0 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0__PRIV_LEVEL_MASK     0x0000a7bc /*       */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL                        10:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_INIT                  0x603 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_0                0x603 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_1                0x423 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_2                0x621 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_3                0x40b /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_4                0x429 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_5                0x4a1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_6                0x681 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_7                0x407 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_8                0x40d /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_9                0x419 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_10               0x431 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_11               0x461 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_12               0x4c1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_13               0x581 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_14               0x701 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CG                                               0x0000a4b0 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_CG_IDLE_CG_DLY_CNT                                      5:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_CG_IDLE_CG_DLY_CNT_HWINIT                              0x02 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CG_IDLE_CG_DLY_CNT__PROD                               0x02 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CG_IDLE_CG_DLY_CNT__MIN_LIMIT                          0x02 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_IDLE_CG_EN                                           6:6 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_CG_IDLE_CG_EN_ENABLED                                   0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CG_IDLE_CG_EN_DISABLED                                  0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CG_IDLE_CG_EN__PROD                                     0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CG_STATE_CG_EN                                          7:7 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_STATE_CG_EN_ENABLED                                  0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_STATE_CG_EN_DISABLED                                 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_STATE_CG_EN__PROD                                    0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_STALL_CG_DLY_CNT                                    13:8 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_STALL_CG_DLY_CNT_HWINIT                             0x02 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_STALL_CG_DLY_CNT__PROD                              0x02 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_STALL_CG_EN                                        14:14 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_CG_STALL_CG_EN_ENABLED                                  0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CG_STALL_CG_EN_DISABLED                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CG_STALL_CG_EN__PROD                                    0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CG_QUIESCENT_CG_EN                                    15:15 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_QUIESCENT_CG_EN_ENABLED                              0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_QUIESCENT_CG_EN_DISABLED                             0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_QUIESCENT_CG_EN__PROD                                0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_WAKEUP_DLY_CNT                                     19:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_CG_WAKEUP_DLY_CNT_HWINIT                                0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CG_WAKEUP_DLY_CNT__PROD                                 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CG_WAKEUP_DLY_CNT__MIN_LIMIT                            0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_THROT_CLK_CNT                                      23:20 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_THROT_CLK_CNT_FULLSPEED                              0xf /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_THROT_CLK_CNT__PROD                                  0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_DI_DT_SKEW_VAL                                     27:24 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_DI_DT_SKEW_VAL_HWINIT                                0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_DI_DT_SKEW_VAL__PROD                                 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_THROT_CLK_EN                                       28:28 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_THROT_CLK_EN_ENABLED                                 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_THROT_CLK_EN_DISABLED                                0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_THROT_CLK_EN__PROD                                   0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_THROT_CLK_SW_OVER                                  29:29 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_THROT_CLK_SW_OVER_EN                                 0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_THROT_CLK_SW_OVER_DIS                                0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_THROT_CLK_SW_OVER__PROD                              0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_PAUSE_CG_EN                                        30:30 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_PAUSE_CG_EN_ENABLED                                  0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_PAUSE_CG_EN_DISABLED                                 0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_PAUSE_CG_EN__PROD                                    0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_HALT_CG_EN                                         31:31 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_HALT_CG_EN_ENABLED                                   0x1 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_HALT_CG_EN_DISABLED                                  0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG_HALT_CG_EN__PROD                                     0x0 /*       */
#define NV_PFB_HSMMU1_PRI_MMU_CG1                                              0x0000a4b4 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_CG1_MONITOR_CG_EN                                       0:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_CG1_MONITOR_CG_EN_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CG1_MONITOR_CG_EN_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CG1_MONITOR_CG_EN__PROD                                 0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CG1_SLCG                                               11:1 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_CG1_SLCG_ENABLED                                      0x000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_CG1_SLCG_DISABLED                                     0x7ff /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_CG1_SLCG__PROD                                        0x000 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PG                                               0x0000a4b8 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_PG_IDLE_BLPG_DLY_CNT                                    7:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PG_IDLE_BLPG_DLY_CNT_HWINIT                            0x0a /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_ELPG_EN_OFFSET_CNT                                  15:8 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PG_ELPG_EN_OFFSET_CNT_HWINIT                           0x0a /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_IDLE_BLPG_EN                                       16:16 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PG_IDLE_BLPG_EN_ENABLED                                 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_IDLE_BLPG_EN_DISABLED                                0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_DIS_EARLY_WUP                                      17:17 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PG_DIS_EARLY_WUP_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_DIS_EARLY_WUP_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_DEEP_ELPG_EN                                       18:18 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PG_DEEP_ELPG_EN_ENABLED                                 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_DEEP_ELPG_EN_DISABLED                                0x0 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_IDLE_ELPG_EN                                       19:19 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PG_IDLE_ELPG_EN_ENABLED                                 0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_IDLE_ELPG_EN_DISABLED                                0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_DIDT_DELAY                                         23:20 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PG_DIDT_DELAY_HWINIT                                    0xa /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_RESET_DURATION                                     26:24 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PG_RESET_DURATION_HWINIT                                0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_CLAMP_DELAY                                        29:27 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PG_CLAMP_DELAY_HWINIT                                   0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_ZONE_OFF_MASK                                      30:30 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PG_ZONE_OFF_MASK_HWINIT                                 0x1 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_SOFT_GATING_EN                                     31:31 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PG_SOFT_GATING_EN_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU1_PRI_MMU_PG_SOFT_GATING_EN_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PG1                                              0x0000a4c0 /* RW-4R */
#define NV_PFB_HSMMU1_PRI_MMU_PG1_ZONE_SEQ                                           23:0 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PG1_ZONE_SEQ_HWINIT                                0x053977 /* RWE-V */
#define NV_PFB_HSMMU1_PRI_MMU_PG1_ZONE_MASK                                         31:24 /* RWEVF */
#define NV_PFB_HSMMU1_PRI_MMU_PG1_ZONE_MASK_HWINIT                                   0xff /* RWE-V */
#define NV_PFB_HSMMU2                                               0x0011c3ff:0x0011c000 /* RW--D */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_ATOM_SIZE                                4096
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_ATOM_SIZE_LG2                             0xC
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_0                           0x603
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_1                           0x623
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_2                           0x623
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_3                           0x62B
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_4                           0x62B
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_5                           0x6A3
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_6                           0x6A3
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_7                           0x62F
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_8                           0x62F
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_9                           0x63B
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_10                          0x63B
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_11                          0x6E3
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_12                          0x6E3
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_13                          0x7A3
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_SWIZID_MASK_14                          0x7A3
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK                             0x0011c0d8 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION                    3:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0             0:0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1             1:1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2             2:2 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3             3:3 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION                   7:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0            4:4 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1            5:5 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2            6:6 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3            7:7 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION                     8:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR        0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON          0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION                    9:9 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR       0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON         0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL              10:10 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED        0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED        0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL             11:11 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED       0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED       0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_ENABLE                    31:12 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL                                             0x0011c080 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL__PRIV_LEVEL_MASK                            0x0011c0d8 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_VM_PG_SIZE                                         0:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_VM_PG_SIZE_128KB                                   0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_VM_PG_SIZE_64KB                                    0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_COMP_FAULT                                         2:2 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_COMP_FAULT_ENABLED                                 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_COMP_FAULT_DISABLED                                0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_MISS_GRAN                                          4:3 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_MISS_GRAN_FULL                                     0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_MISS_GRAN_HALF                                     0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_MISS_GRAN_QUARTER                                  0x2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_MISS_GRAN_NO_PTE_COMP                              0x3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_CACHE_MODE                                         6:5 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_CACHE_MODE_ON                                      0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS                     0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS                      0x2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_CACHE_MODE_OFF                                     0x3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_L2_SEND_MODE                                       9:9 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_L2_SEND_MODE_ONE_PTE                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_L2_SEND_MODE_WHOLE_CL                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE                           25:24 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_L2                          0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC                      0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_RMW                         0x2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_POWER                       0x3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA                            26:26 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_OFF                          0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_ON                           0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_CACHE_MODE_PHYS                                  29:28 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_CACHE_MODE_PHYS_ON                                 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_CACHE_MODE_PHYS_EVICT_SMPG_PARTIALS                0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_CACHE_MODE_PHYS_EVICT_ALL_PARTIALS                 0x2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CTRL_CACHE_MODE_PHYS_OFF                                0x3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL                                         0x0011c0a0 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_UTLB_SIZE                                      1:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_UTLB_SIZE_INIT                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_UTLB_RB_SIZE                                   3:2 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_UTLB_RB_SIZE_INIT                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_NVL_L1TLB_SIZE                                 5:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_NVL_L1TLB_SIZE_INIT                            0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_NVL_L1TLB_FA_SIZE                              7:6 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_NVL_L1TLB_FA_SIZE_INIT                         0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_NVL_L1TLB_RB_SIZE                              9:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_NVL_L1TLB_RB_SIZE_INIT                         0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_BIG_PG                   11:10 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_BIG_PG_INIT                0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_SMALL_PG                 13:12 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_SMALL_PG_INIT              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_NVL_UTLB_SIZE                                15:14 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_NVL_UTLB_SIZE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_L1TLB_SIZE                                   17:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_L1TLB_SIZE_INIT                                0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_L1TLB_FA_SIZE                                19:18 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_L1TLB_FA_SIZE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_L1TLB_RB_SIZE                                21:20 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_L1TLB_RB_SIZE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_BIG_PG                       23:22 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_BIG_PG_INIT                    0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_SMALL_PG                     25:24 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_SMALL_PG_INIT                  0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE                      26:26 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE_FALSE                  0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE_TRUE                   0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE                       27:27 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE_FALSE                   0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE_TRUE                    0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_NVL_UTLB_RB_SIZE                             29:28 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_NVL_UTLB_RB_SIZE_INIT                          0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_SECURE_LOCK                                  30:30 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_SECURE_LOCK_FALSE                              0x0 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_SECURE_LOCK_INIT                               0x0 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_SECURE_LOCK_TRUE                               0x1 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE                    31:31 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE_TRUE                 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE_FALSE                0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_MISC                                         0x0011c0a8 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_MISC_UTLB_UF                                        2:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_MISC_UTLB_UF_INIT                                   0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_MISC_L1TLB_UF                                       5:3 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_MISC_L1TLB_UF_INIT                                  0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_MISC_NVL_UTLB_UF                                    8:6 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_MISC_NVL_UTLB_UF_INIT                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_MISC_NVL_L1TLB_UF                                  11:9 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_TLB_MISC_NVL_L1TLB_UF_INIT                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CAPABILITIES                                     0x0011c0ac /* R--4R */
#define NV_PFB_HSMMU2_PRI_MMU_CAPABILITIES_CE                                         0:0 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_CAPABILITIES_CE_YES                                     0x1 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_CAPABILITIES_CE_NO                                      0x0 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_CAPABILITIES_NVLINK                                     1:1 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_CAPABILITIES_NVLINK_YES                                 0x1 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_CAPABILITIES_NVLINK_NO                                  0x0 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_CAPABILITIES_CHI                                        2:2 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_CAPABILITIES_CHI_YES                                    0x1 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_CAPABILITIES_CHI_NO                                     0x0 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_CAPABILITIES_PCIE                                       3:3 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_CAPABILITIES_PCIE_YES                                   0x1 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_CAPABILITIES_PCIE_NO                                    0x0 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH                                         0x0011c0a4 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_DISABLE                                  0:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_DISABLE_FALSE                            0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_DISABLE_TRUE                             0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_BIG_DISABLE                                    1:1 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_BIG_DISABLE_FALSE                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_BIG_DISABLE_TRUE                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_UNFILLED_DISABLE                               2:2 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_UNFILLED_DISABLE_FALSE                         0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_UNFILLED_DISABLE_TRUE                          0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_ENABLE                                         3:3 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_ENABLE_TRUE                                    0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_INCR_ONLY                                      4:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_INCR_ONLY_FALSE                                0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_INCR_ONLY_TRUE                                 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL                             5:5 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL_FALSE                       0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL_TRUE                        0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_ATSGPA_DISABLE                                 6:6 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_ATSGPA_DISABLE_FALSE                           0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_ATSGPA_DISABLE_TRUE                            0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE                               7:7 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE_FALSE                         0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE_TRUE                          0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH                           12:12 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_DISABLE                     0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_ENABLE                      0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE                         15:13 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_1                         0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_2                         0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_4                         0x2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_8                         0x3 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_16                        0x4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_32                        0x5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_64                        0x6 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE                            16:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE_FALSE                        0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE_TRUE                         0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_BIG_DISABLE                              17:17 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_BIG_DISABLE_FALSE                          0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_BIG_DISABLE_TRUE                           0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE                         18:18 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE_FALSE                     0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE_TRUE                      0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_ENABLE                                   19:19 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_ENABLE_TRUE                                0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_INCR_ONLY                                20:20 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_INCR_ONLY_FALSE                            0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_INCR_ONLY_TRUE                             0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_PREF_ON_FILL                       21:21 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_PREF_ON_FILL_FALSE                   0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_PREF_ON_FILL_TRUE                    0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_ATSGPA_DISABLE                           22:22 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_ATSGPA_DISABLE_FALSE                       0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_ATSGPA_DISABLE_TRUE                        0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SRIOVGPA_DISABLE                         23:23 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SRIOVGPA_DISABLE_FALSE                     0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SRIOVGPA_DISABLE_TRUE                      0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH                       28:28 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH_DISABLE                 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH_ENABLE                  0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE                     31:29 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_1                     0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_2                     0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_4                     0x2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_8                     0x3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_16                    0x4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_32                    0x5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_64                    0x6 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_CTRL                                       0x0011c0c4 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_CTRL_WR_KIND                                      7:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_CTRL_WR_KIND_INIT                                0x00 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_CTRL_RD_KIND                                     15:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_CTRL_RD_KIND_INIT                                0x00 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_CTRL_DEBUG                                      16:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_CTRL_DEBUG_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_CTRL_DEBUG_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_CTRL_PAGE_SIZE                                  18:17 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_4KB                                0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_64KB                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_128KB                              0x2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_1MB                                0x3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_WR                                         0x0011c0c8 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_WR_APERTURE                                       1:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_WR_APERTURE_PEER_MEM                              0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_C                             0x2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_NC                            0x3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_WR_VOL                                            2:2 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_WR_VOL_FALSE                                      0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_WR_VOL_TRUE                                       0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_WR_ADDR                                          31:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_WR_ADDR_INIT                                0x0000000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT                           0x000000c /*       */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_RD                                         0x0011c0cc /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_RD_APERTURE                                       1:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_RD_APERTURE_PEER_MEM                              0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_C                             0x2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_NC                            0x3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_RD_VOL                                            2:2 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_RD_VOL_FALSE                                      0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_RD_VOL_TRUE                                       0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_RD_ADDR                                          31:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_RD_ADDR_INIT                                0x0000000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT                           0x000000c /*       */
#define NV_PFB_HSMMU2_PRI_MMU_PM                                               0x0011c084 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT                                               7:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_00                                       0x00 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_01                                       0x01 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_02                                       0x02 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_03                                       0x03 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_04                                       0x04 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_05                                       0x05 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_06                                       0x06 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_07                                       0x07 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_08                                       0x08 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_09                                       0x09 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_0A                                       0x0a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_0B                                       0x0b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_0C                                       0x0c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_0D                                       0x0d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_0E                                       0x0e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_0F                                       0x0f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_10                                       0x10 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_11                                       0x11 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_12                                       0x12 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_13                                       0x13 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_14                                       0x14 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_15                                       0x15 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_16                                       0x16 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_17                                       0x17 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_18                                       0x18 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_19                                       0x19 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_1A                                       0x1a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_1B                                       0x1b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_1C                                       0x1c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_1D                                       0x1d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_1E                                       0x1e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_1F                                       0x1f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_20                                       0x20 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_21                                       0x21 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_22                                       0x22 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_23                                       0x23 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_24                                       0x24 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_25                                       0x25 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_26                                       0x26 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_27                                       0x27 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_28                                       0x28 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_29                                       0x29 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_2A                                       0x2a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_2B                                       0x2b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_2C                                       0x2c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_2D                                       0x2d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_2E                                       0x2e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_2F                                       0x2f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_30                                       0x30 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_31                                       0x31 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_32                                       0x32 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_33                                       0x33 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_34                                       0x34 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_35                                       0x35 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_36                                       0x36 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_37                                       0x37 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_38                                       0x38 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_39                                       0x39 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_3A                                       0x3a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_3B                                       0x3b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_3C                                       0x3c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_3D                                       0x3d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_3E                                       0x3e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_3F                                       0x3f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_40                                       0x40 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_41                                       0x41 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_42                                       0x42 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_43                                       0x43 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_44                                       0x44 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_45                                       0x45 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_46                                       0x46 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_47                                       0x47 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_48                                       0x48 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_49                                       0x49 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_4A                                       0x4a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_4B                                       0x4b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_4C                                       0x4c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_4D                                       0x4d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_4E                                       0x4e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_4F                                       0x4f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_50                                       0x50 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_51                                       0x51 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_52                                       0x52 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_53                                       0x53 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_54                                       0x54 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_55                                       0x55 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_56                                       0x56 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_57                                       0x57 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_58                                       0x58 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_59                                       0x59 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_5A                                       0x5a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_5B                                       0x5b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_5C                                       0x5c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_5D                                       0x5d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_5E                                       0x5e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_5F                                       0x5f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_60                                       0x60 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_61                                       0x61 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_62                                       0x62 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_63                                       0x63 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_64                                       0x64 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_65                                       0x65 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_66                                       0x66 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_67                                       0x67 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_68                                       0x68 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_69                                       0x69 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_6A                                       0x6a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_6B                                       0x6b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_6C                                       0x6c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_6D                                       0x6d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_6E                                       0x6e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_6F                                       0x6f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_70                                       0x70 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_71                                       0x71 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_72                                       0x72 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_73                                       0x73 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_74                                       0x74 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_75                                       0x75 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_76                                       0x76 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_77                                       0x77 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_78                                       0x78 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_79                                       0x79 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_7A                                       0x7a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_7B                                       0x7b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_7C                                       0x7c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_7D                                       0x7d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_7E                                       0x7e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_7F                                       0x7f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_80                                       0x80 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_81                                       0x81 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_82                                       0x82 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_83                                       0x83 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_84                                       0x84 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_85                                       0x85 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_86                                       0x86 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_87                                       0x87 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_88                                       0x88 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_89                                       0x89 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_8A                                       0x8a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_8B                                       0x8b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_8C                                       0x8c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_8D                                       0x8d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_8E                                       0x8e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_8F                                       0x8f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_90                                       0x90 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_91                                       0x91 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_92                                       0x92 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_93                                       0x93 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_94                                       0x94 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_95                                       0x95 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_96                                       0x96 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_97                                       0x97 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_98                                       0x98 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_99                                       0x99 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_9A                                       0x9a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_9B                                       0x9b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_9C                                       0x9c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_9D                                       0x9d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_9E                                       0x9e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_9F                                       0x9f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_A0                                       0xa0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_A1                                       0xa1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_A2                                       0xa2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_A3                                       0xa3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_A4                                       0xa4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_A5                                       0xa5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_A6                                       0xa6 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_A7                                       0xa7 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_A8                                       0xa8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_A9                                       0xa9 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_AA                                       0xaa /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_AB                                       0xab /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_AC                                       0xac /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_AD                                       0xad /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_AE                                       0xae /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_AF                                       0xaf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_B0                                       0xb0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_B1                                       0xb1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_B2                                       0xb2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_B3                                       0xb3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_B4                                       0xb4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_B5                                       0xb5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_B6                                       0xb6 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_B7                                       0xb7 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_B8                                       0xb8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_B9                                       0xb9 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_BA                                       0xba /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_BB                                       0xbb /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_BC                                       0xbc /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_BD                                       0xbd /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_BE                                       0xbe /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_BF                                       0xbf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_C0                                       0xc0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_C1                                       0xc1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_C2                                       0xc2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_C3                                       0xc3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_C4                                       0xc4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_C5                                       0xc5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_C6                                       0xc6 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_C7                                       0xc7 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_C8                                       0xc8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_C9                                       0xc9 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_CA                                       0xca /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_CB                                       0xcb /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_CC                                       0xcc /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_CD                                       0xcd /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_CE                                       0xce /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_CF                                       0xcf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_D0                                       0xd0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_D1                                       0xd1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_D2                                       0xd2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_D3                                       0xd3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_D4                                       0xd4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_D5                                       0xd5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_D6                                       0xd6 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_D7                                       0xd7 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_D8                                       0xd8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_D9                                       0xd9 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_DA                                       0xda /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_DB                                       0xdb /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_DC                                       0xdc /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_DD                                       0xdd /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_DE                                       0xde /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_DF                                       0xdf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_E0                                       0xe0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_E1                                       0xe1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_E2                                       0xe2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_E3                                       0xe3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_E4                                       0xe4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_E5                                       0xe5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_E6                                       0xe6 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_E7                                       0xe7 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_E8                                       0xe8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_E9                                       0xe9 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_EA                                       0xea /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_EB                                       0xeb /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_EC                                       0xec /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_ED                                       0xed /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_EE                                       0xee /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_EF                                       0xef /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_F0                                       0xf0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_F1                                       0xf1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_F2                                       0xf2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_F3                                       0xf3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_F4                                       0xf4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_F5                                       0xf5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_F6                                       0xf6 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_F7                                       0xf7 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_F8                                       0xf8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_F9                                       0xf9 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_FA                                       0xfa /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_FB                                       0xfb /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_FC                                       0xfc /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_GRP_FD                                       0xfd /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_STATIC_PATTERN_5_4_GROUP                     0xfe /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_STATIC_PATTERN_A_4_GROUP                     0xff /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1                                         15:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_00                                  0x00 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_01                                  0x01 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_02                                  0x02 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_03                                  0x03 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_04                                  0x04 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_05                                  0x05 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_06                                  0x06 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_07                                  0x07 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_08                                  0x08 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_09                                  0x09 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_0A                                  0x0a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_0B                                  0x0b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_0C                                  0x0c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_0D                                  0x0d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_0E                                  0x0e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_0F                                  0x0f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_10                                  0x10 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_11                                  0x11 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_12                                  0x12 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_13                                  0x13 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_14                                  0x14 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_15                                  0x15 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_16                                  0x16 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_17                                  0x17 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_18                                  0x18 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_19                                  0x19 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_1A                                  0x1a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_1B                                  0x1b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_1C                                  0x1c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_1D                                  0x1d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_1E                                  0x1e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_1F                                  0x1f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_20                                  0x20 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_21                                  0x21 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_22                                  0x22 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_23                                  0x23 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_24                                  0x24 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_25                                  0x25 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_26                                  0x26 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_27                                  0x27 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_28                                  0x28 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_29                                  0x29 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_2A                                  0x2a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_2B                                  0x2b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_2C                                  0x2c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_2D                                  0x2d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_2E                                  0x2e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_2F                                  0x2f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_30                                  0x30 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_31                                  0x31 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_32                                  0x32 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_33                                  0x33 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_34                                  0x34 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_35                                  0x35 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_36                                  0x36 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_37                                  0x37 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_38                                  0x38 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_39                                  0x39 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_3A                                  0x3a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_3B                                  0x3b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_3C                                  0x3c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_3D                                  0x3d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_3E                                  0x3e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_3F                                  0x3f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_40                                  0x40 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_41                                  0x41 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_42                                  0x42 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_43                                  0x43 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_44                                  0x44 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_45                                  0x45 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_46                                  0x46 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_47                                  0x47 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_48                                  0x48 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_49                                  0x49 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_4A                                  0x4a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_4B                                  0x4b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_4C                                  0x4c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_4D                                  0x4d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_4E                                  0x4e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_4F                                  0x4f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_50                                  0x50 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_51                                  0x51 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_52                                  0x52 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_53                                  0x53 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_54                                  0x54 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_55                                  0x55 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_56                                  0x56 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_57                                  0x57 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_58                                  0x58 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_59                                  0x59 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_5A                                  0x5a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_5B                                  0x5b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_5C                                  0x5c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_5D                                  0x5d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_5E                                  0x5e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_5F                                  0x5f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_60                                  0x60 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_61                                  0x61 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_62                                  0x62 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_63                                  0x63 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_64                                  0x64 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_65                                  0x65 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_66                                  0x66 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_67                                  0x67 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_68                                  0x68 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_69                                  0x69 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_6A                                  0x6a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_6B                                  0x6b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_6C                                  0x6c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_6D                                  0x6d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_6E                                  0x6e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_6F                                  0x6f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_70                                  0x70 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_71                                  0x71 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_72                                  0x72 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_73                                  0x73 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_74                                  0x74 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_75                                  0x75 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_76                                  0x76 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_77                                  0x77 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_78                                  0x78 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_79                                  0x79 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_7A                                  0x7a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_7B                                  0x7b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_7C                                  0x7c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_7D                                  0x7d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_7E                                  0x7e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_7F                                  0x7f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_80                                  0x80 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_81                                  0x81 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_82                                  0x82 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_83                                  0x83 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_84                                  0x84 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_85                                  0x85 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_86                                  0x86 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_87                                  0x87 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_88                                  0x88 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_89                                  0x89 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_8A                                  0x8a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_8B                                  0x8b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_8C                                  0x8c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_8D                                  0x8d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_8E                                  0x8e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_8F                                  0x8f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_90                                  0x90 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_91                                  0x91 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_92                                  0x92 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_93                                  0x93 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_94                                  0x94 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_95                                  0x95 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_96                                  0x96 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_97                                  0x97 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_98                                  0x98 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_99                                  0x99 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_9A                                  0x9a /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_9B                                  0x9b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_9C                                  0x9c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_9D                                  0x9d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_9E                                  0x9e /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_9F                                  0x9f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_A0                                  0xa0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_A1                                  0xa1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_A2                                  0xa2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_A3                                  0xa3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_A4                                  0xa4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_A5                                  0xa5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_A6                                  0xa6 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_A7                                  0xa7 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_A8                                  0xa8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_A9                                  0xa9 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_AA                                  0xaa /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_AB                                  0xab /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_AC                                  0xac /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_AD                                  0xad /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_AE                                  0xae /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_AF                                  0xaf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_B0                                  0xb0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_B1                                  0xb1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_B2                                  0xb2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_B3                                  0xb3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_B4                                  0xb4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_B5                                  0xb5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_B6                                  0xb6 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_B7                                  0xb7 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_B8                                  0xb8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_B9                                  0xb9 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_BA                                  0xba /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_BB                                  0xbb /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_BC                                  0xbc /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_BD                                  0xbd /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_BE                                  0xbe /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_BF                                  0xbf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_C0                                  0xc0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_C1                                  0xc1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_C2                                  0xc2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_C3                                  0xc3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_C4                                  0xc4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_C5                                  0xc5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_C6                                  0xc6 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_C7                                  0xc7 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_C8                                  0xc8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_C9                                  0xc9 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_CA                                  0xca /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_CB                                  0xcb /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_CC                                  0xcc /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_CD                                  0xcd /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_CE                                  0xce /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_CF                                  0xcf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_D0                                  0xd0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_D1                                  0xd1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_D2                                  0xd2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_D3                                  0xd3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_D4                                  0xd4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_D5                                  0xd5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_D6                                  0xd6 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_D7                                  0xd7 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_D8                                  0xd8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_D9                                  0xd9 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_DA                                  0xda /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_DB                                  0xdb /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_DC                                  0xdc /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_DD                                  0xdd /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_DE                                  0xde /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_DF                                  0xdf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_E0                                  0xe0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_E1                                  0xe1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_E2                                  0xe2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_E3                                  0xe3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_E4                                  0xe4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_E5                                  0xe5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_E6                                  0xe6 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_E7                                  0xe7 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_E8                                  0xe8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_E9                                  0xe9 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_EA                                  0xea /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_EB                                  0xeb /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_EC                                  0xec /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_ED                                  0xed /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_EE                                  0xee /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_EF                                  0xef /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_F0                                  0xf0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_F1                                  0xf1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_F2                                  0xf2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_F3                                  0xf3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_F4                                  0xf4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_F5                                  0xf5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_F6                                  0xf6 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_F7                                  0xf7 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_F8                                  0xf8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_F9                                  0xf9 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_FA                                  0xfa /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_FB                                  0xfb /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_FC                                  0xfc /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_GRP_FD                                  0xfd /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_5_4_GROUP                0xfe /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_A_4_GROUP                0xff /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_BLK_ACT                                            30:30 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_BLK_ACT_DISABLE                                      0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_BLK_ACT_ENABLE                                       0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_BLK_ACT_INIT                                         0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_ENABLE                                             31:31 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_ENABLE_DISABLE                                       0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_ENABLE_ENABLE                                        0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_ENABLE_INIT                                          0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_ADDR_LOW                                      0x0011c088 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_PM_ADDR_LOW_ALIGNMENT                            0x00000008 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_PM_ADDR_LOW_BITS                                       31:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_ADDR_LOW_BITS_INIT                            0x00000000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UPPER_ADDR_LOW                                0x0011c08c /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UPPER_ADDR_LOW_BITS                                 23:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UPPER_ADDR_LOW_BITS_INIT                        0x000000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_ADDR_HIGH                                     0x0011c090 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_PM_ADDR_HIGH_ALIGNMENT                           0x00000008 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_PM_ADDR_HIGH_BITS                                      31:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_ADDR_HIGH_BITS_INIT                           0x00000000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UPPER_ADDR_HIGH                               0x0011c094 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS                                23:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS_INIT                       0x000000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK                                     0x0011c098 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE0                                        0:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE0_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE0_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE1                                        1:1 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE1_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE1_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE2                                        2:2 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE2_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE2_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE3                                        3:3 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE3_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE3_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE4                                        4:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE4_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE4_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE5                                        5:5 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE5_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE5_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE6                                        6:6 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE6_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE6_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE7                                        7:7 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE7_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE7_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE8                                        8:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE8_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE8_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE9                                        9:9 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE9_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE9_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE10                                     10:10 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE10_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE10_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE11                                     11:11 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE11_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE11_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE12                                     12:12 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE12_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE12_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE13                                     13:13 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE13_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE13_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE14                                     14:14 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE14_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE14_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE15                                     15:15 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE15_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_CE15_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL0                                     16:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL0_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL0_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL1                                     17:17 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL1_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL1_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL2                                     18:18 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL2_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL2_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL3                                     19:19 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL3_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL3_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL4                                     20:20 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL4_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL4_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL5                                     21:21 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL5_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL5_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL6                                     22:22 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL6_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL6_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL7                                     23:23 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL7_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL7_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL8                                     24:24 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL8_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL8_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL9                                     25:25 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL9_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL9_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL10                                    26:26 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL10_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL10_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL11                                    27:27 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL11_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL11_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL12                                    28:28 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL12_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL12_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL13                                    29:29 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL13_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL13_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL14                                    30:30 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL14_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL14_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL15                                    31:31 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL15_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_UNIT_MASK_NVL15_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK                                      0x0011c09c /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_RD                                          0:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_RD_DISABLED                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_RD_ENABLED                                  0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_WR                                          1:1 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_WR_DISABLED                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_WR_ENABLED                                  0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_GATOM                                       2:2 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_GATOM_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_GATOM_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_GRED                                        3:3 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_GRED_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_GRED_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_CACHE_MGMT                                  4:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_DISABLED                         0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_ENABLED                          0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PREFETCH                                    5:5 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PREFETCH_DISABLED                           0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PREFETCH_ENABLED                            0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH                                6:6 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_DISABLED                       0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_ENABLED                        0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_MEMBAR                                      7:7 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_MEMBAR_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_MEMBAR_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PHYS_RD                                     8:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PHYS_RD_DISABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PHYS_RD_ENABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PHYS_WR                                     9:9 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PHYS_WR_DISABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PHYS_WR_ENABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PHYS_GRED                                 10:10 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PHYS_GRED_DISABLED                          0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PHYS_GRED_ENABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PHYS_GATOM                                11:11 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_DISABLED                         0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_ENABLED                          0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PACK_RD                                   12:12 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PACK_RD_DISABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PACK_RD_ENABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_CONCAT_WR                                 13:13 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_CONCAT_WR_DISABLED                          0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_CONCAT_WR_ENABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_CONCAT_GRED                               14:14 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_DISABLED                        0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_ENABLED                         0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM                              15:15 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_DISABLED                       0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_ENABLED                        0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_MULTICAST                                 16:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_MULTICAST_DISABLED                          0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_MULTICAST_ENABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_RDMC                                      17:17 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_RDMC_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_RDMC_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR                         18:18 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR_DISABLED                  0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR_ENABLED                   0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED                       19:19 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED_DISABLED                0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED_ENABLED                 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM                      20:20 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM_DISABLED               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM_ENABLED                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS                               22:22 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_DISABLED                        0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_ENABLED                         0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS                              23:23 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_DISABLED                       0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_ENABLED                        0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_VIDMEM                                    24:24 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_VIDMEM_ENABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_VIDMEM_DISABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PEER                                      25:25 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PEER_ENABLED                                0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_PEER_DISABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_SYSMEM_C                                  26:26 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_SYSMEM_C_ENABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_SYSMEM_C_DISABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_SYSMEM_NC                                 27:27 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_ENABLED                           0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_DISABLED                          0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_TYPE                                      30:30 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_TYPE_VIRTUAL                                0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_TYPE_PHYSICAL                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_EXCLUSIVE                                 31:31 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_FALSE                             0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_TRUE                              0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK                 0x0011c0dc /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_CFG0                                        0x0011c0d4 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_CFG0__PRIV_LEVEL_MASK                       0x0011c0d8 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE                                  2:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_32MB                             0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_64MB                             0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_128MB                            0x2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_256MB                            0x3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_512MB                            0x4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_1024MB                           0x5 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_INIT                             0x3 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID                           31:16 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID_INIT                     0x0400 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_SRIOV_VMMU_TABLE(i)                      (0x0011c160+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU2_PRI_MMU_SRIOV_VMMU_TABLE__SIZE_1                                 32 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SRIOV_VMMU_TABLE__PRIV_LEVEL_MASK                0x0011c0d8 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP                                31:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP_INIT                     0x00000000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID(i)              (0x0011c218+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU2_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID__SIZE_1                         32 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID__PRIV_LEVEL_MASK        0x0011c0d8 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID_BITMAP                        31:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID_BITMAP_INIT             0xffffffff /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK                              0x0011c3fc /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION                     3:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL  0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED  0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0              0:0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1              1:1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2              2:2 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3              3:3 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION                    7:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0              0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1              0xc /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0             4:4 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1             5:5 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2             6:6 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3             7:7 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION                      8:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR         0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON           0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION                     9:9 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR        0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON          0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL               10:10 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED         0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED         0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL              11:11 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED        0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED        0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE                     31:12 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CONTROL                           0x0011c3f8 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK          0x0011c3fc /*       */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR             4:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK        0x1 /* RW--T */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT        0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP        0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR           5:5 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK      0x1 /* RW--T */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT      0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP      0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS                            0x0011c3f4 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA       0:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA     1:1 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA       2:2 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA     3:3 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_SA_DATA      4:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_SA_DATA    5:5 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_FA_DATA      6:6 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_FA_DATA    7:7 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_SA_DATA      8:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_SA_DATA    9:9 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_FA_DATA    10:10 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_FA_DATA  11:11 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_SA_DATA    12:12 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_SA_DATA  13:13 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_FA_DATA    14:14 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_FA_DATA  15:15 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET                           30:30 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_CLEAR                       0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_TASK                        0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_INIT                        0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT               0x0011c3f0 /* R--4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL               15:0 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT        0x0000 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE             31:16 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT             0x0011c3ec /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL             15:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT      0x0000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE           31:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS                           0x0011c3e8 /* R--4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_INDEX                           31:0 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_CACHELINE                       15:0 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_ERROR_MASK                     27:16 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID                         31:28 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA             0x0 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA             0x1 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB0_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB0_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB1_SA_DATA            0x2 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB1_FA_DATA            0x3 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB2_SA_DATA            0x4 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB2_FA_DATA            0x5 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB3_SA_DATA            0x6 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB3_FA_DATA            0x7 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CONTROL                           0x0011c3e4 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK          0x0011c3fc /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR             4:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK        0x1 /* RW--T */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT        0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP        0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR           5:5 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK      0x1 /* RW--T */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT      0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP      0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CONTROL                          0x0011c2b4 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CONTROL__PRIV_LEVEL_MASK         0x0011c3fc /*       */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR            4:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK       0x1 /* RW--T */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT       0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP       0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR          5:5 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK     0x1 /* RW--T */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT     0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP     0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS                           0x0011c2b8 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET                          30:30 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET_CLEAR                      0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET_TASK                       0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET_INIT                       0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT              0x0011c2bc /* R--4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_TOTAL              15:0 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_UNIQUE            31:16 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT      0x0000 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT            0x0011c2c0 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_TOTAL            15:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_UNIQUE          31:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT    0x0000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS                          0x0011c2c4 /* R--4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_INDEX                          31:0 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_CACHELINE                      15:0 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_ERROR_MASK                    27:16 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_RAM_ID                        31:28 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CONTROL                          0x0011c2c8 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CONTROL__PRIV_LEVEL_MASK         0x0011c3fc /*       */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR            4:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK       0x1 /* RW--T */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT       0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP       0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR          5:5 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK     0x1 /* RW--T */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT     0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP     0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS                           0x0011c2cc /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET                          30:30 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET_CLEAR                      0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET_TASK                       0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET_INIT                       0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT              0x0011c2d0 /* R--4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_TOTAL              15:0 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_UNIQUE            31:16 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT      0x0000 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT            0x0011c2d4 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_TOTAL            15:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_UNIQUE          31:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT    0x0000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS                          0x0011c2d8 /* R--4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_INDEX                          31:0 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_CACHELINE                      15:0 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_ERROR_MASK                    27:16 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_RAM_ID                        31:28 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CONTROL                          0x0011c2dc /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CONTROL__PRIV_LEVEL_MASK         0x0011c3fc /*       */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR            4:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK       0x1 /* RW--T */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT       0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP       0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR          5:5 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK     0x1 /* RW--T */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT     0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP     0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS                           0x0011c2e0 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET                          30:30 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET_CLEAR                      0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET_TASK                       0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET_INIT                       0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT              0x0011c2e4 /* R--4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_TOTAL              15:0 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_UNIQUE            31:16 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT      0x0000 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT            0x0011c2e8 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_TOTAL            15:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_UNIQUE          31:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT    0x0000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS                          0x0011c2ec /* R--4R */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_INDEX                          31:0 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_CACHELINE                      15:0 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_ERROR_MASK                    27:16 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_RAM_ID                        31:28 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS                            0x0011c3e0 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA       0:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA     1:1 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA       2:2 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA     3:3 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET                           30:30 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_CLEAR                       0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_TASK                        0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_INIT                        0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT               0x0011c3dc /* R--4R */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL               15:0 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT        0x0000 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE             31:16 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT             0x0011c3d8 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL             15:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT      0x0000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE           31:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS                           0x0011c3d4 /* R--4R */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_INDEX                           31:0 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_CACHELINE                       11:0 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_ERROR_MASK                     27:12 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID                         31:28 /* R-XVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA             0x0 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA             0x1 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUBMMU_GLOBAL_ESR                              0x0011c3d0 /* R--4R */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR                   0:0 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_NOT_PENDING       0x0 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_PENDING           0x1 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR                 1:1 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_NOT_PENDING     0x0 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_PENDING         0x1 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_ERROR_CONTAINMENT_CONTROL                        0x0011c3c0 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_ERROR_CONTAINMENT_CONTROL__PRIV_LEVEL_MASK       0x0011c3fc /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_REISSUE                 0:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_REISSUE_ENABLE          0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_REISSUE_DISABLE         0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_BLACKLIST               1:1 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_BLACKLIST_ENABLE        0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_BLACKLIST_DISABLE       0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER(i)        (0x0011c0e0+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1                    8 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__PRIV_LEVEL_MASK  0x0011c0dc /*       */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL                     31:0 /* RWEUF */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_INIT          0x00000000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_INVALID       0x00000000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB0        0x00000001 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB1        0x00000002 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB2        0x00000004 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB3        0x00000008 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB4        0x00000010 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB5        0x00000020 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB6        0x00000040 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB7        0x00000080 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB8        0x00000100 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB9        0x00000200 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB10       0x00000400 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB11       0x00000800 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB12       0x00001000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB13       0x00002000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB14       0x00004000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB15       0x00008000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_ALL_HSHUBS    0x0000001f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_PCIE          0x00000001 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_565MODE       0x80000000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_464MODE       0x40000000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG                      0x0011c100 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG__PRIV_LEVEL_MASK     0x0011c0dc /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS                        31:0 /* RWEUF */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INVALID          0x00000000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB0      0x00000001 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB1      0x00000002 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB2      0x00000004 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB3      0x00000008 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB4      0x00000010 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB5      0x00000020 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB6      0x00000040 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB7      0x00000080 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB8      0x00000100 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB9      0x00000200 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB10     0x00000400 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB11     0x00000800 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB12     0x00001000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB13     0x00002000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB14     0x00004000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB15     0x00008000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_BOTH_HSHUBS      0x00000003 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ALL_HSHUBS       0x0000001f /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_PCIE             0x00000001 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INIT             0x00000001 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK                        0x0011c108 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION               3:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0        0:0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1        1:1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2        2:2 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3        3:3 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION              7:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "gin_intr_ctrl" /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0        0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1        0xc /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0       4:4 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1       5:5 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2       6:6 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3       7:7 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION                8:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR   0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON     0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION               9:9 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR  0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON    0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL         10:10 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED   0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED   0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL        11:11 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED  0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED  0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE               31:12 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_gin_intr_ctrl_wr_secure" /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL         0xfffff /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE        0x00000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL                                        0x0011c10c /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL__PRIV_LEVEL_MASK                       0x0011c108 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_MESSAGE                                      31:0 /* RWEUF */
#define NV_PFB_HSMMU2_PRI_MMU_INTR_CTRL_MESSAGE_0_INIT                         0xc0000080 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT                                0x0011c110 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_NUM_RANGE_CHECKER              0x00000008 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE                                  3:0 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE_INIT                             0x2 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE                        29:29 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_CLEAR                    0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_SET                      0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_MODE                                30:30 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_ACCESS                           0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_DIRTY                            0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE                              31:31 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_FALSE                          0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_TRUE                           0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_INIT                           0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO(i)       (0x0011c114+(i)*8) /* RW-4A */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO__SIZE_1                   8 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_GRANULARITY             3:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_GRANULARITY_INIT        0x5 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL                   31:24 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL_INIT               0x00 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI(i)       (0x0011c118+(i)*8) /* RW-4A */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI__SIZE_1                   8 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL                    31:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL_INIT         0x00000000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL                                     0x0011c158 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL__PRIV_LEVEL_MASK                    0x0011c0d8 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE                     2:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_L2                  0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC              0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_RMW                 0x2 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_POWER               0x3 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_PCIE                0x4 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA                      4:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA_OFF                  0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA_ON                   0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE            5:5 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_L2         0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_FOLLOW_SYS_COH 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32                       8:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32_DISABLED              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32_ENABLED               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64                       9:9 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64_DISABLED              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64_ENABLED               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32                          10:10 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32_DISABLED                   0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32_ENABLED                    0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64                          11:11 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64_DISABLED                   0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64_ENABLED                    0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32              12:12 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32_DISABLED       0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32_ENABLED        0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64              13:13 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64_DISABLED       0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64_ENABLED        0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS                                  0x0011c15c /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS__PRIV_LEVEL_MASK                 0x0011c0dc /*       */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_V                                       6:0 /* R--VF */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_COUNT                                   6:0 /* R--VF */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE                             13:8 /* R--VF */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_ZERO                        0x00 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_TWO                         0x02 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_FOUR                        0x04 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_EIGHT                       0x08 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK                            23:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_INIT                        0x00 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER(i)        ((i)+16):((i)+16) /*       */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER__SIZE_1                   8 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_ENABLED                 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_DISABLED                0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_INIT                    0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2                24:24 /* R-EVF */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT             0x0 /* R-E-V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_ENABLED          0x1 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_DISABLED         0x0 /* R---V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM                            25:25 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_INIT                         0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_ENABLED                      0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_DISABLED                     0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE                          26:26 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_INIT                       0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_PEER                       0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_SYSMEM                     0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK                      27:27 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK_INIT                   0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK_ENABLED                0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK_DISABLED               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_NUM_ACTIVE_LTCS_SLICES_PER_LTC                        30:28 /* R--VF */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK       0x0011c2f0 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK(i)       (0x0011c2f4+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK__SIZE_1                  32 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK__PRIV_LEVEL_MASK 0x0011c2f0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK_BITMAP                 31:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK_BITMAP_INIT      0xffffffff /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK                   0x0011c2a8 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION          3:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0   0:0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1   1:1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2   2:2 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3   3:3 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION         7:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0   0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1   0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0  4:4 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1  5:5 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2  6:6 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3  7:7 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION           8:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION          9:9 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL    10:10 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL   11:11 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE          31:12 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK                     0x0011c2ac /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0     0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1     0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CC_GFID_TEE_STATE_ENABLE(i)              (0x0011c298+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU2_PRI_MMU_CC_GFID_TEE_STATE_ENABLE__SIZE_1                          2 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CC_GFID_TEE_STATE_ENABLE__PRIV_LEVEL_MASK        0x0011c2a8 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CC_GFID_TEE_STATE_ENABLE_BITMASK                       31:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_CC_GFID_TEE_STATE_ENABLE_BITMASK_INIT            0x00000000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE(i)                          (0x0011c2a0+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE__SIZE_1                                      2 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE__PRIV_LEVEL_MASK                    0x0011c2ac /*       */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_BITMASK                                   31:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_GFID_DISABLE_BITMASK_INIT                        0x00000000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK                    0x0011c3bc /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION           3:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0    0:0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1    1:1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2    2:2 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3    3:3 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION          7:4 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0   4:4 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1   5:5 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2   6:6 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3   7:7 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION            8:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION           9:9 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL     10:10 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL    11:11 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_ENABLE           31:12 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOTTOM                             0x0011c3b8 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOTTOM__PRIV_LEVEL_MASK            0x0011c3bc /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOTTOM_PER_SLICE                         19:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOTTOM_PER_SLICE_INIT                 0x00000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_MIDDLE                             0x0011c3b4 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_MIDDLE__PRIV_LEVEL_MASK            0x0011c3bc /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE                         19:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_INIT                 0x00000 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE            0x01000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE_LG2        0x0000c /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0                      0x0011c3b0 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0__PRIV_LEVEL_MASK     0x0011c3bc /*       */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL                        10:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_INIT                  0x603 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_0                0x603 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_1                0x423 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_2                0x621 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_3                0x40b /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_4                0x429 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_5                0x4a1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_6                0x681 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_7                0x407 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_8                0x40d /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_9                0x419 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_10               0x431 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_11               0x461 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_12               0x4c1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_13               0x581 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_14               0x701 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CG                                               0x0011c0b0 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_CG_IDLE_CG_DLY_CNT                                      5:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_CG_IDLE_CG_DLY_CNT_HWINIT                              0x02 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CG_IDLE_CG_DLY_CNT__PROD                               0x02 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CG_IDLE_CG_DLY_CNT__MIN_LIMIT                          0x02 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_IDLE_CG_EN                                           6:6 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_CG_IDLE_CG_EN_ENABLED                                   0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CG_IDLE_CG_EN_DISABLED                                  0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CG_IDLE_CG_EN__PROD                                     0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CG_STATE_CG_EN                                          7:7 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_STATE_CG_EN_ENABLED                                  0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_STATE_CG_EN_DISABLED                                 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_STATE_CG_EN__PROD                                    0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_STALL_CG_DLY_CNT                                    13:8 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_STALL_CG_DLY_CNT_HWINIT                             0x02 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_STALL_CG_DLY_CNT__PROD                              0x02 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_STALL_CG_EN                                        14:14 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_CG_STALL_CG_EN_ENABLED                                  0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CG_STALL_CG_EN_DISABLED                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CG_STALL_CG_EN__PROD                                    0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CG_QUIESCENT_CG_EN                                    15:15 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_QUIESCENT_CG_EN_ENABLED                              0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_QUIESCENT_CG_EN_DISABLED                             0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_QUIESCENT_CG_EN__PROD                                0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_WAKEUP_DLY_CNT                                     19:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_CG_WAKEUP_DLY_CNT_HWINIT                                0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CG_WAKEUP_DLY_CNT__PROD                                 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CG_WAKEUP_DLY_CNT__MIN_LIMIT                            0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_THROT_CLK_CNT                                      23:20 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_THROT_CLK_CNT_FULLSPEED                              0xf /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_THROT_CLK_CNT__PROD                                  0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_DI_DT_SKEW_VAL                                     27:24 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_DI_DT_SKEW_VAL_HWINIT                                0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_DI_DT_SKEW_VAL__PROD                                 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_THROT_CLK_EN                                       28:28 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_THROT_CLK_EN_ENABLED                                 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_THROT_CLK_EN_DISABLED                                0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_THROT_CLK_EN__PROD                                   0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_THROT_CLK_SW_OVER                                  29:29 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_THROT_CLK_SW_OVER_EN                                 0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_THROT_CLK_SW_OVER_DIS                                0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_THROT_CLK_SW_OVER__PROD                              0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_PAUSE_CG_EN                                        30:30 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_PAUSE_CG_EN_ENABLED                                  0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_PAUSE_CG_EN_DISABLED                                 0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_PAUSE_CG_EN__PROD                                    0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_HALT_CG_EN                                         31:31 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_HALT_CG_EN_ENABLED                                   0x1 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_HALT_CG_EN_DISABLED                                  0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG_HALT_CG_EN__PROD                                     0x0 /*       */
#define NV_PFB_HSMMU2_PRI_MMU_CG1                                              0x0011c0b4 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_CG1_MONITOR_CG_EN                                       0:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_CG1_MONITOR_CG_EN_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CG1_MONITOR_CG_EN_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CG1_MONITOR_CG_EN__PROD                                 0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CG1_SLCG                                               11:1 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_CG1_SLCG_ENABLED                                      0x000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_CG1_SLCG_DISABLED                                     0x7ff /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_CG1_SLCG__PROD                                        0x000 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PG                                               0x0011c0b8 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_PG_IDLE_BLPG_DLY_CNT                                    7:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PG_IDLE_BLPG_DLY_CNT_HWINIT                            0x0a /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_ELPG_EN_OFFSET_CNT                                  15:8 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PG_ELPG_EN_OFFSET_CNT_HWINIT                           0x0a /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_IDLE_BLPG_EN                                       16:16 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PG_IDLE_BLPG_EN_ENABLED                                 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_IDLE_BLPG_EN_DISABLED                                0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_DIS_EARLY_WUP                                      17:17 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PG_DIS_EARLY_WUP_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_DIS_EARLY_WUP_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_DEEP_ELPG_EN                                       18:18 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PG_DEEP_ELPG_EN_ENABLED                                 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_DEEP_ELPG_EN_DISABLED                                0x0 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_IDLE_ELPG_EN                                       19:19 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PG_IDLE_ELPG_EN_ENABLED                                 0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_IDLE_ELPG_EN_DISABLED                                0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_DIDT_DELAY                                         23:20 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PG_DIDT_DELAY_HWINIT                                    0xa /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_RESET_DURATION                                     26:24 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PG_RESET_DURATION_HWINIT                                0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_CLAMP_DELAY                                        29:27 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PG_CLAMP_DELAY_HWINIT                                   0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_ZONE_OFF_MASK                                      30:30 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PG_ZONE_OFF_MASK_HWINIT                                 0x1 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_SOFT_GATING_EN                                     31:31 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PG_SOFT_GATING_EN_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU2_PRI_MMU_PG_SOFT_GATING_EN_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PG1                                              0x0011c0c0 /* RW-4R */
#define NV_PFB_HSMMU2_PRI_MMU_PG1_ZONE_SEQ                                           23:0 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PG1_ZONE_SEQ_HWINIT                                0x053977 /* RWE-V */
#define NV_PFB_HSMMU2_PRI_MMU_PG1_ZONE_MASK                                         31:24 /* RWEVF */
#define NV_PFB_HSMMU2_PRI_MMU_PG1_ZONE_MASK_HWINIT                                   0xff /* RWE-V */
#define NV_PFB_HSMMU3                                               0x0011c7ff:0x0011c400 /* RW--D */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_ATOM_SIZE                                4096
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_ATOM_SIZE_LG2                             0xC
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_0                           0x603
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_1                           0x623
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_2                           0x623
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_3                           0x62B
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_4                           0x62B
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_5                           0x6A3
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_6                           0x6A3
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_7                           0x62F
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_8                           0x62F
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_9                           0x63B
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_10                          0x63B
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_11                          0x6E3
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_12                          0x6E3
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_13                          0x7A3
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_SWIZID_MASK_14                          0x7A3
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK                             0x0011c4d8 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION                    3:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0             0:0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1             1:1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2             2:2 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3             3:3 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION                   7:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0            4:4 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1            5:5 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2            6:6 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3            7:7 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE     0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE    0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION                     8:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR        0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON          0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION                    9:9 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR       0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON         0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL              10:10 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED        0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED        0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL             11:11 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED       0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED       0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_ENABLE                    31:12 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL                                             0x0011c480 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL__PRIV_LEVEL_MASK                            0x0011c4d8 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_VM_PG_SIZE                                         0:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_VM_PG_SIZE_128KB                                   0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_VM_PG_SIZE_64KB                                    0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_COMP_FAULT                                         2:2 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_COMP_FAULT_ENABLED                                 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_COMP_FAULT_DISABLED                                0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_MISS_GRAN                                          4:3 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_MISS_GRAN_FULL                                     0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_MISS_GRAN_HALF                                     0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_MISS_GRAN_QUARTER                                  0x2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_MISS_GRAN_NO_PTE_COMP                              0x3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_CACHE_MODE                                         6:5 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_CACHE_MODE_ON                                      0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS                     0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS                      0x2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_CACHE_MODE_OFF                                     0x3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_L2_SEND_MODE                                       9:9 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_L2_SEND_MODE_ONE_PTE                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_L2_SEND_MODE_WHOLE_CL                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE                           25:24 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_L2                          0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC                      0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_RMW                         0x2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_POWER                       0x3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA                            26:26 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_OFF                          0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_ON                           0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_CACHE_MODE_PHYS                                  29:28 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_CACHE_MODE_PHYS_ON                                 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_CACHE_MODE_PHYS_EVICT_SMPG_PARTIALS                0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_CACHE_MODE_PHYS_EVICT_ALL_PARTIALS                 0x2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CTRL_CACHE_MODE_PHYS_OFF                                0x3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL                                         0x0011c4a0 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_UTLB_SIZE                                      1:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_UTLB_SIZE_INIT                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_UTLB_RB_SIZE                                   3:2 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_UTLB_RB_SIZE_INIT                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_NVL_L1TLB_SIZE                                 5:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_NVL_L1TLB_SIZE_INIT                            0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_NVL_L1TLB_FA_SIZE                              7:6 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_NVL_L1TLB_FA_SIZE_INIT                         0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_NVL_L1TLB_RB_SIZE                              9:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_NVL_L1TLB_RB_SIZE_INIT                         0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_BIG_PG                   11:10 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_BIG_PG_INIT                0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_SMALL_PG                 13:12 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_SMALL_PG_INIT              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_NVL_UTLB_SIZE                                15:14 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_NVL_UTLB_SIZE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_L1TLB_SIZE                                   17:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_L1TLB_SIZE_INIT                                0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_L1TLB_FA_SIZE                                19:18 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_L1TLB_FA_SIZE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_L1TLB_RB_SIZE                                21:20 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_L1TLB_RB_SIZE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_BIG_PG                       23:22 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_BIG_PG_INIT                    0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_SMALL_PG                     25:24 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_SMALL_PG_INIT                  0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE                      26:26 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE_FALSE                  0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE_TRUE                   0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE                       27:27 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE_FALSE                   0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE_TRUE                    0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_NVL_UTLB_RB_SIZE                             29:28 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_NVL_UTLB_RB_SIZE_INIT                          0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_SECURE_LOCK                                  30:30 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_SECURE_LOCK_FALSE                              0x0 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_SECURE_LOCK_INIT                               0x0 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_SECURE_LOCK_TRUE                               0x1 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE                    31:31 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE_TRUE                 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE_FALSE                0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_MISC                                         0x0011c4a8 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_MISC_UTLB_UF                                        2:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_MISC_UTLB_UF_INIT                                   0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_MISC_L1TLB_UF                                       5:3 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_MISC_L1TLB_UF_INIT                                  0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_MISC_NVL_UTLB_UF                                    8:6 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_MISC_NVL_UTLB_UF_INIT                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_MISC_NVL_L1TLB_UF                                  11:9 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_TLB_MISC_NVL_L1TLB_UF_INIT                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CAPABILITIES                                     0x0011c4ac /* R--4R */
#define NV_PFB_HSMMU3_PRI_MMU_CAPABILITIES_CE                                         0:0 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_CAPABILITIES_CE_YES                                     0x1 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_CAPABILITIES_CE_NO                                      0x0 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_CAPABILITIES_NVLINK                                     1:1 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_CAPABILITIES_NVLINK_YES                                 0x1 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_CAPABILITIES_NVLINK_NO                                  0x0 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_CAPABILITIES_CHI                                        2:2 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_CAPABILITIES_CHI_YES                                    0x1 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_CAPABILITIES_CHI_NO                                     0x0 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_CAPABILITIES_PCIE                                       3:3 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_CAPABILITIES_PCIE_YES                                   0x1 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_CAPABILITIES_PCIE_NO                                    0x0 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH                                         0x0011c4a4 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_DISABLE                                  0:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_DISABLE_FALSE                            0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_DISABLE_TRUE                             0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_BIG_DISABLE                                    1:1 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_BIG_DISABLE_FALSE                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_BIG_DISABLE_TRUE                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_UNFILLED_DISABLE                               2:2 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_UNFILLED_DISABLE_FALSE                         0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_UNFILLED_DISABLE_TRUE                          0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_ENABLE                                         3:3 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_ENABLE_TRUE                                    0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_INCR_ONLY                                      4:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_INCR_ONLY_FALSE                                0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_INCR_ONLY_TRUE                                 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL                             5:5 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL_FALSE                       0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_PREF_ON_FILL_TRUE                        0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_ATSGPA_DISABLE                                 6:6 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_ATSGPA_DISABLE_FALSE                           0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_ATSGPA_DISABLE_TRUE                            0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE                               7:7 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE_FALSE                         0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SRIOVGPA_DISABLE_TRUE                          0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH                           12:12 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_DISABLE                     0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_ENABLE                      0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE                         15:13 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_1                         0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_2                         0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_4                         0x2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_8                         0x3 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_16                        0x4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_32                        0x5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_64                        0x6 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE                            16:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE_FALSE                        0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE_TRUE                         0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_BIG_DISABLE                              17:17 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_BIG_DISABLE_FALSE                          0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_BIG_DISABLE_TRUE                           0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE                         18:18 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE_FALSE                     0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE_TRUE                      0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_ENABLE                                   19:19 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_ENABLE_TRUE                                0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_INCR_ONLY                                20:20 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_INCR_ONLY_FALSE                            0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_INCR_ONLY_TRUE                             0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_PREF_ON_FILL                       21:21 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_PREF_ON_FILL_FALSE                   0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_PREF_ON_FILL_TRUE                    0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_ATSGPA_DISABLE                           22:22 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_ATSGPA_DISABLE_FALSE                       0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_ATSGPA_DISABLE_TRUE                        0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SRIOVGPA_DISABLE                         23:23 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SRIOVGPA_DISABLE_FALSE                     0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SRIOVGPA_DISABLE_TRUE                      0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH                       28:28 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH_DISABLE                 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH_ENABLE                  0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE                     31:29 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_1                     0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_2                     0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_4                     0x2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_8                     0x3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_16                    0x4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_32                    0x5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_64                    0x6 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_CTRL                                       0x0011c4c4 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_CTRL_WR_KIND                                      7:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_CTRL_WR_KIND_INIT                                0x00 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_CTRL_RD_KIND                                     15:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_CTRL_RD_KIND_INIT                                0x00 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_CTRL_DEBUG                                      16:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_CTRL_DEBUG_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_CTRL_DEBUG_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_CTRL_PAGE_SIZE                                  18:17 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_4KB                                0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_64KB                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_128KB                              0x2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_1MB                                0x3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_WR                                         0x0011c4c8 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_WR_APERTURE                                       1:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_WR_APERTURE_PEER_MEM                              0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_C                             0x2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_NC                            0x3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_WR_VOL                                            2:2 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_WR_VOL_FALSE                                      0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_WR_VOL_TRUE                                       0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_WR_ADDR                                          31:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_WR_ADDR_INIT                                0x0000000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT                           0x000000c /*       */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_RD                                         0x0011c4cc /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_RD_APERTURE                                       1:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_RD_APERTURE_PEER_MEM                              0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_C                             0x2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_NC                            0x3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_RD_VOL                                            2:2 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_RD_VOL_FALSE                                      0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_RD_VOL_TRUE                                       0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_RD_ADDR                                          31:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_RD_ADDR_INIT                                0x0000000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT                           0x000000c /*       */
#define NV_PFB_HSMMU3_PRI_MMU_PM                                               0x0011c484 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT                                               7:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_00                                       0x00 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_01                                       0x01 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_02                                       0x02 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_03                                       0x03 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_04                                       0x04 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_05                                       0x05 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_06                                       0x06 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_07                                       0x07 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_08                                       0x08 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_09                                       0x09 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_0A                                       0x0a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_0B                                       0x0b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_0C                                       0x0c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_0D                                       0x0d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_0E                                       0x0e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_0F                                       0x0f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_10                                       0x10 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_11                                       0x11 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_12                                       0x12 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_13                                       0x13 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_14                                       0x14 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_15                                       0x15 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_16                                       0x16 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_17                                       0x17 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_18                                       0x18 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_19                                       0x19 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_1A                                       0x1a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_1B                                       0x1b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_1C                                       0x1c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_1D                                       0x1d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_1E                                       0x1e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_1F                                       0x1f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_20                                       0x20 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_21                                       0x21 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_22                                       0x22 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_23                                       0x23 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_24                                       0x24 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_25                                       0x25 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_26                                       0x26 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_27                                       0x27 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_28                                       0x28 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_29                                       0x29 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_2A                                       0x2a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_2B                                       0x2b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_2C                                       0x2c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_2D                                       0x2d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_2E                                       0x2e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_2F                                       0x2f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_30                                       0x30 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_31                                       0x31 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_32                                       0x32 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_33                                       0x33 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_34                                       0x34 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_35                                       0x35 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_36                                       0x36 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_37                                       0x37 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_38                                       0x38 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_39                                       0x39 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_3A                                       0x3a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_3B                                       0x3b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_3C                                       0x3c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_3D                                       0x3d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_3E                                       0x3e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_3F                                       0x3f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_40                                       0x40 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_41                                       0x41 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_42                                       0x42 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_43                                       0x43 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_44                                       0x44 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_45                                       0x45 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_46                                       0x46 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_47                                       0x47 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_48                                       0x48 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_49                                       0x49 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_4A                                       0x4a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_4B                                       0x4b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_4C                                       0x4c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_4D                                       0x4d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_4E                                       0x4e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_4F                                       0x4f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_50                                       0x50 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_51                                       0x51 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_52                                       0x52 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_53                                       0x53 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_54                                       0x54 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_55                                       0x55 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_56                                       0x56 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_57                                       0x57 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_58                                       0x58 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_59                                       0x59 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_5A                                       0x5a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_5B                                       0x5b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_5C                                       0x5c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_5D                                       0x5d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_5E                                       0x5e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_5F                                       0x5f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_60                                       0x60 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_61                                       0x61 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_62                                       0x62 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_63                                       0x63 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_64                                       0x64 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_65                                       0x65 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_66                                       0x66 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_67                                       0x67 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_68                                       0x68 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_69                                       0x69 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_6A                                       0x6a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_6B                                       0x6b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_6C                                       0x6c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_6D                                       0x6d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_6E                                       0x6e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_6F                                       0x6f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_70                                       0x70 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_71                                       0x71 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_72                                       0x72 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_73                                       0x73 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_74                                       0x74 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_75                                       0x75 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_76                                       0x76 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_77                                       0x77 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_78                                       0x78 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_79                                       0x79 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_7A                                       0x7a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_7B                                       0x7b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_7C                                       0x7c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_7D                                       0x7d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_7E                                       0x7e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_7F                                       0x7f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_80                                       0x80 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_81                                       0x81 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_82                                       0x82 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_83                                       0x83 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_84                                       0x84 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_85                                       0x85 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_86                                       0x86 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_87                                       0x87 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_88                                       0x88 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_89                                       0x89 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_8A                                       0x8a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_8B                                       0x8b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_8C                                       0x8c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_8D                                       0x8d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_8E                                       0x8e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_8F                                       0x8f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_90                                       0x90 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_91                                       0x91 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_92                                       0x92 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_93                                       0x93 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_94                                       0x94 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_95                                       0x95 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_96                                       0x96 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_97                                       0x97 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_98                                       0x98 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_99                                       0x99 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_9A                                       0x9a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_9B                                       0x9b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_9C                                       0x9c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_9D                                       0x9d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_9E                                       0x9e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_9F                                       0x9f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_A0                                       0xa0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_A1                                       0xa1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_A2                                       0xa2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_A3                                       0xa3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_A4                                       0xa4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_A5                                       0xa5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_A6                                       0xa6 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_A7                                       0xa7 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_A8                                       0xa8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_A9                                       0xa9 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_AA                                       0xaa /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_AB                                       0xab /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_AC                                       0xac /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_AD                                       0xad /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_AE                                       0xae /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_AF                                       0xaf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_B0                                       0xb0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_B1                                       0xb1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_B2                                       0xb2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_B3                                       0xb3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_B4                                       0xb4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_B5                                       0xb5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_B6                                       0xb6 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_B7                                       0xb7 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_B8                                       0xb8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_B9                                       0xb9 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_BA                                       0xba /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_BB                                       0xbb /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_BC                                       0xbc /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_BD                                       0xbd /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_BE                                       0xbe /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_BF                                       0xbf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_C0                                       0xc0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_C1                                       0xc1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_C2                                       0xc2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_C3                                       0xc3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_C4                                       0xc4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_C5                                       0xc5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_C6                                       0xc6 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_C7                                       0xc7 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_C8                                       0xc8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_C9                                       0xc9 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_CA                                       0xca /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_CB                                       0xcb /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_CC                                       0xcc /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_CD                                       0xcd /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_CE                                       0xce /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_CF                                       0xcf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_D0                                       0xd0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_D1                                       0xd1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_D2                                       0xd2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_D3                                       0xd3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_D4                                       0xd4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_D5                                       0xd5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_D6                                       0xd6 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_D7                                       0xd7 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_D8                                       0xd8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_D9                                       0xd9 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_DA                                       0xda /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_DB                                       0xdb /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_DC                                       0xdc /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_DD                                       0xdd /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_DE                                       0xde /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_DF                                       0xdf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_E0                                       0xe0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_E1                                       0xe1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_E2                                       0xe2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_E3                                       0xe3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_E4                                       0xe4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_E5                                       0xe5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_E6                                       0xe6 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_E7                                       0xe7 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_E8                                       0xe8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_E9                                       0xe9 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_EA                                       0xea /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_EB                                       0xeb /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_EC                                       0xec /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_ED                                       0xed /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_EE                                       0xee /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_EF                                       0xef /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_F0                                       0xf0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_F1                                       0xf1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_F2                                       0xf2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_F3                                       0xf3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_F4                                       0xf4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_F5                                       0xf5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_F6                                       0xf6 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_F7                                       0xf7 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_F8                                       0xf8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_F9                                       0xf9 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_FA                                       0xfa /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_FB                                       0xfb /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_FC                                       0xfc /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_GRP_FD                                       0xfd /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_STATIC_PATTERN_5_4_GROUP                     0xfe /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_STATIC_PATTERN_A_4_GROUP                     0xff /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1                                         15:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_00                                  0x00 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_01                                  0x01 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_02                                  0x02 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_03                                  0x03 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_04                                  0x04 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_05                                  0x05 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_06                                  0x06 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_07                                  0x07 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_08                                  0x08 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_09                                  0x09 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_0A                                  0x0a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_0B                                  0x0b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_0C                                  0x0c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_0D                                  0x0d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_0E                                  0x0e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_0F                                  0x0f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_10                                  0x10 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_11                                  0x11 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_12                                  0x12 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_13                                  0x13 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_14                                  0x14 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_15                                  0x15 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_16                                  0x16 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_17                                  0x17 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_18                                  0x18 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_19                                  0x19 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_1A                                  0x1a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_1B                                  0x1b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_1C                                  0x1c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_1D                                  0x1d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_1E                                  0x1e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_1F                                  0x1f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_20                                  0x20 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_21                                  0x21 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_22                                  0x22 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_23                                  0x23 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_24                                  0x24 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_25                                  0x25 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_26                                  0x26 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_27                                  0x27 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_28                                  0x28 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_29                                  0x29 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_2A                                  0x2a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_2B                                  0x2b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_2C                                  0x2c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_2D                                  0x2d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_2E                                  0x2e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_2F                                  0x2f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_30                                  0x30 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_31                                  0x31 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_32                                  0x32 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_33                                  0x33 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_34                                  0x34 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_35                                  0x35 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_36                                  0x36 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_37                                  0x37 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_38                                  0x38 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_39                                  0x39 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_3A                                  0x3a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_3B                                  0x3b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_3C                                  0x3c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_3D                                  0x3d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_3E                                  0x3e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_3F                                  0x3f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_40                                  0x40 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_41                                  0x41 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_42                                  0x42 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_43                                  0x43 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_44                                  0x44 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_45                                  0x45 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_46                                  0x46 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_47                                  0x47 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_48                                  0x48 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_49                                  0x49 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_4A                                  0x4a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_4B                                  0x4b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_4C                                  0x4c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_4D                                  0x4d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_4E                                  0x4e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_4F                                  0x4f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_50                                  0x50 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_51                                  0x51 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_52                                  0x52 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_53                                  0x53 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_54                                  0x54 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_55                                  0x55 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_56                                  0x56 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_57                                  0x57 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_58                                  0x58 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_59                                  0x59 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_5A                                  0x5a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_5B                                  0x5b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_5C                                  0x5c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_5D                                  0x5d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_5E                                  0x5e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_5F                                  0x5f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_60                                  0x60 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_61                                  0x61 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_62                                  0x62 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_63                                  0x63 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_64                                  0x64 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_65                                  0x65 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_66                                  0x66 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_67                                  0x67 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_68                                  0x68 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_69                                  0x69 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_6A                                  0x6a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_6B                                  0x6b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_6C                                  0x6c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_6D                                  0x6d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_6E                                  0x6e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_6F                                  0x6f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_70                                  0x70 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_71                                  0x71 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_72                                  0x72 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_73                                  0x73 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_74                                  0x74 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_75                                  0x75 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_76                                  0x76 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_77                                  0x77 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_78                                  0x78 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_79                                  0x79 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_7A                                  0x7a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_7B                                  0x7b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_7C                                  0x7c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_7D                                  0x7d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_7E                                  0x7e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_7F                                  0x7f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_80                                  0x80 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_81                                  0x81 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_82                                  0x82 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_83                                  0x83 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_84                                  0x84 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_85                                  0x85 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_86                                  0x86 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_87                                  0x87 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_88                                  0x88 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_89                                  0x89 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_8A                                  0x8a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_8B                                  0x8b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_8C                                  0x8c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_8D                                  0x8d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_8E                                  0x8e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_8F                                  0x8f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_90                                  0x90 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_91                                  0x91 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_92                                  0x92 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_93                                  0x93 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_94                                  0x94 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_95                                  0x95 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_96                                  0x96 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_97                                  0x97 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_98                                  0x98 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_99                                  0x99 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_9A                                  0x9a /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_9B                                  0x9b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_9C                                  0x9c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_9D                                  0x9d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_9E                                  0x9e /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_9F                                  0x9f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_A0                                  0xa0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_A1                                  0xa1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_A2                                  0xa2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_A3                                  0xa3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_A4                                  0xa4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_A5                                  0xa5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_A6                                  0xa6 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_A7                                  0xa7 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_A8                                  0xa8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_A9                                  0xa9 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_AA                                  0xaa /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_AB                                  0xab /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_AC                                  0xac /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_AD                                  0xad /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_AE                                  0xae /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_AF                                  0xaf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_B0                                  0xb0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_B1                                  0xb1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_B2                                  0xb2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_B3                                  0xb3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_B4                                  0xb4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_B5                                  0xb5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_B6                                  0xb6 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_B7                                  0xb7 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_B8                                  0xb8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_B9                                  0xb9 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_BA                                  0xba /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_BB                                  0xbb /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_BC                                  0xbc /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_BD                                  0xbd /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_BE                                  0xbe /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_BF                                  0xbf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_C0                                  0xc0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_C1                                  0xc1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_C2                                  0xc2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_C3                                  0xc3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_C4                                  0xc4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_C5                                  0xc5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_C6                                  0xc6 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_C7                                  0xc7 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_C8                                  0xc8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_C9                                  0xc9 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_CA                                  0xca /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_CB                                  0xcb /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_CC                                  0xcc /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_CD                                  0xcd /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_CE                                  0xce /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_CF                                  0xcf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_D0                                  0xd0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_D1                                  0xd1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_D2                                  0xd2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_D3                                  0xd3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_D4                                  0xd4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_D5                                  0xd5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_D6                                  0xd6 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_D7                                  0xd7 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_D8                                  0xd8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_D9                                  0xd9 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_DA                                  0xda /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_DB                                  0xdb /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_DC                                  0xdc /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_DD                                  0xdd /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_DE                                  0xde /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_DF                                  0xdf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_E0                                  0xe0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_E1                                  0xe1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_E2                                  0xe2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_E3                                  0xe3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_E4                                  0xe4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_E5                                  0xe5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_E6                                  0xe6 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_E7                                  0xe7 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_E8                                  0xe8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_E9                                  0xe9 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_EA                                  0xea /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_EB                                  0xeb /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_EC                                  0xec /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_ED                                  0xed /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_EE                                  0xee /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_EF                                  0xef /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_F0                                  0xf0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_F1                                  0xf1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_F2                                  0xf2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_F3                                  0xf3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_F4                                  0xf4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_F5                                  0xf5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_F6                                  0xf6 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_F7                                  0xf7 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_F8                                  0xf8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_F9                                  0xf9 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_FA                                  0xfa /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_FB                                  0xfb /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_FC                                  0xfc /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_GRP_FD                                  0xfd /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_5_4_GROUP                0xfe /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_A_4_GROUP                0xff /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_BLK_ACT                                            30:30 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_BLK_ACT_DISABLE                                      0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_BLK_ACT_ENABLE                                       0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_BLK_ACT_INIT                                         0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_ENABLE                                             31:31 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_ENABLE_DISABLE                                       0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_ENABLE_ENABLE                                        0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_ENABLE_INIT                                          0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_ADDR_LOW                                      0x0011c488 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_PM_ADDR_LOW_ALIGNMENT                            0x00000008 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_PM_ADDR_LOW_BITS                                       31:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_ADDR_LOW_BITS_INIT                            0x00000000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UPPER_ADDR_LOW                                0x0011c48c /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UPPER_ADDR_LOW_BITS                                 23:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UPPER_ADDR_LOW_BITS_INIT                        0x000000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_ADDR_HIGH                                     0x0011c490 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_PM_ADDR_HIGH_ALIGNMENT                           0x00000008 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_PM_ADDR_HIGH_BITS                                      31:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_ADDR_HIGH_BITS_INIT                           0x00000000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UPPER_ADDR_HIGH                               0x0011c494 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS                                23:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS_INIT                       0x000000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK                                     0x0011c498 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE0                                        0:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE0_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE0_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE1                                        1:1 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE1_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE1_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE2                                        2:2 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE2_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE2_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE3                                        3:3 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE3_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE3_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE4                                        4:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE4_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE4_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE5                                        5:5 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE5_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE5_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE6                                        6:6 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE6_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE6_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE7                                        7:7 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE7_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE7_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE8                                        8:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE8_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE8_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE9                                        9:9 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE9_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE9_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE10                                     10:10 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE10_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE10_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE11                                     11:11 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE11_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE11_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE12                                     12:12 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE12_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE12_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE13                                     13:13 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE13_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE13_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE14                                     14:14 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE14_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE14_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE15                                     15:15 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE15_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_CE15_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL0                                     16:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL0_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL0_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL1                                     17:17 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL1_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL1_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL2                                     18:18 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL2_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL2_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL3                                     19:19 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL3_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL3_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL4                                     20:20 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL4_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL4_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL5                                     21:21 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL5_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL5_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL6                                     22:22 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL6_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL6_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL7                                     23:23 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL7_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL7_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL8                                     24:24 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL8_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL8_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL9                                     25:25 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL9_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL9_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL10                                    26:26 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL10_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL10_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL11                                    27:27 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL11_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL11_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL12                                    28:28 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL12_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL12_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL13                                    29:29 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL13_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL13_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL14                                    30:30 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL14_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL14_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL15                                    31:31 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL15_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_UNIT_MASK_NVL15_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK                                      0x0011c49c /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_RD                                          0:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_RD_DISABLED                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_RD_ENABLED                                  0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_WR                                          1:1 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_WR_DISABLED                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_WR_ENABLED                                  0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_GATOM                                       2:2 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_GATOM_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_GATOM_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_GRED                                        3:3 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_GRED_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_GRED_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_CACHE_MGMT                                  4:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_DISABLED                         0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_ENABLED                          0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PREFETCH                                    5:5 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PREFETCH_DISABLED                           0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PREFETCH_ENABLED                            0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH                                6:6 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_DISABLED                       0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_ENABLED                        0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_MEMBAR                                      7:7 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_MEMBAR_DISABLED                             0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_MEMBAR_ENABLED                              0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PHYS_RD                                     8:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PHYS_RD_DISABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PHYS_RD_ENABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PHYS_WR                                     9:9 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PHYS_WR_DISABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PHYS_WR_ENABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PHYS_GRED                                 10:10 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PHYS_GRED_DISABLED                          0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PHYS_GRED_ENABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PHYS_GATOM                                11:11 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_DISABLED                         0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_ENABLED                          0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PACK_RD                                   12:12 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PACK_RD_DISABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PACK_RD_ENABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_CONCAT_WR                                 13:13 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_CONCAT_WR_DISABLED                          0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_CONCAT_WR_ENABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_CONCAT_GRED                               14:14 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_DISABLED                        0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_ENABLED                         0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM                              15:15 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_DISABLED                       0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_ENABLED                        0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_MULTICAST                                 16:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_MULTICAST_DISABLED                          0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_MULTICAST_ENABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_RDMC                                      17:17 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_RDMC_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_RDMC_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR                         18:18 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR_DISABLED                  0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_WR_ENABLED                   0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED                       19:19 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED_DISABLED                0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GRED_ENABLED                 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM                      20:20 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM_DISABLED               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PARTIAL_CONCAT_GATOM_ENABLED                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS                               22:22 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_DISABLED                        0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_ENABLED                         0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS                              23:23 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_DISABLED                       0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_ENABLED                        0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_VIDMEM                                    24:24 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_VIDMEM_ENABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_VIDMEM_DISABLED                             0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PEER                                      25:25 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PEER_ENABLED                                0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_PEER_DISABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_SYSMEM_C                                  26:26 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_SYSMEM_C_ENABLED                            0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_SYSMEM_C_DISABLED                           0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_SYSMEM_NC                                 27:27 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_ENABLED                           0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_DISABLED                          0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_TYPE                                      30:30 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_TYPE_VIRTUAL                                0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_TYPE_PHYSICAL                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_EXCLUSIVE                                 31:31 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_FALSE                             0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_TRUE                              0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK                 0x0011c4dc /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUB_CONNECTION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_CFG0                                        0x0011c4d4 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_CFG0__PRIV_LEVEL_MASK                       0x0011c4d8 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE                                  2:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_32MB                             0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_64MB                             0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_128MB                            0x2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_256MB                            0x3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_512MB                            0x4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_1024MB                           0x5 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_INIT                             0x3 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID                           31:16 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID_INIT                     0x0400 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_SRIOV_VMMU_TABLE(i)                      (0x0011c560+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU3_PRI_MMU_SRIOV_VMMU_TABLE__SIZE_1                                 32 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SRIOV_VMMU_TABLE__PRIV_LEVEL_MASK                0x0011c4d8 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP                                31:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP_INIT                     0x00000000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID(i)              (0x0011c618+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU3_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID__SIZE_1                         32 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID__PRIV_LEVEL_MASK        0x0011c4d8 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID_BITMAP                        31:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_SRIOV_VMMU_SEGMENT_VALID_BITMAP_INIT             0xffffffff /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK                              0x0011c7fc /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION                     3:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL  0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED  0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0              0:0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1              1:1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2              2:2 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3              3:3 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE       0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE      0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION                    7:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0              0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1              0xc /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0             4:4 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1             5:5 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2             6:6 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3             7:7 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE      0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE     0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION                      8:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR         0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON           0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION                     9:9 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR        0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON          0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL               10:10 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED         0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED         0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL              11:11 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED        0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED        0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE                     31:12 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CONTROL                           0x0011c7f8 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK          0x0011c7fc /*       */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR             4:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK        0x1 /* RW--T */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT        0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP        0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR           5:5 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK      0x1 /* RW--T */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT      0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP      0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS                            0x0011c7f4 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA       0:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA     1:1 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA       2:2 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA     3:3 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB0_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB0_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_SA_DATA      4:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_SA_DATA    5:5 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_FA_DATA      6:6 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB1_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_FA_DATA    7:7 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB1_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_SA_DATA      8:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_SA_DATA    9:9 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_FA_DATA    10:10 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB2_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_FA_DATA  11:11 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB2_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_SA_DATA    12:12 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_SA_DATA  13:13 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_FA_DATA    14:14 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB3_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_FA_DATA  15:15 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB3_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET                           30:30 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_CLEAR                       0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_TASK                        0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_INIT                        0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT               0x0011c7f0 /* R--4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL               15:0 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT        0x0000 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE             31:16 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT             0x0011c7ec /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL             15:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT      0x0000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE           31:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS                           0x0011c7e8 /* R--4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_INDEX                           31:0 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_CACHELINE                       15:0 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_ERROR_MASK                     27:16 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID                         31:28 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA             0x0 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA             0x1 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB0_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB0_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB1_SA_DATA            0x2 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB1_FA_DATA            0x3 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB2_SA_DATA            0x4 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB2_FA_DATA            0x5 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB3_SA_DATA            0x6 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB3_FA_DATA            0x7 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CONTROL                           0x0011c7e4 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK          0x0011c7fc /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR             4:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK        0x1 /* RW--T */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT        0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP        0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR           5:5 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK      0x1 /* RW--T */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT      0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP      0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CONTROL                          0x0011c6b4 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CONTROL__PRIV_LEVEL_MASK         0x0011c7fc /*       */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR            4:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK       0x1 /* RW--T */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT       0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP       0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR          5:5 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK     0x1 /* RW--T */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT     0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP     0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS                           0x0011c6b8 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET                          30:30 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET_CLEAR                      0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET_TASK                       0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_STATUS_RESET_INIT                       0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT              0x0011c6bc /* R--4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_TOTAL              15:0 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_UNIQUE            31:16 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT      0x0000 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT            0x0011c6c0 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_TOTAL            15:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_UNIQUE          31:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT    0x0000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS                          0x0011c6c4 /* R--4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_INDEX                          31:0 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_CACHELINE                      15:0 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_ERROR_MASK                    27:16 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_RAM_ID                        31:28 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB1_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CONTROL                          0x0011c6c8 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CONTROL__PRIV_LEVEL_MASK         0x0011c7fc /*       */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR            4:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK       0x1 /* RW--T */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT       0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP       0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR          5:5 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK     0x1 /* RW--T */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT     0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP     0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS                           0x0011c6cc /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET                          30:30 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET_CLEAR                      0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET_TASK                       0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_STATUS_RESET_INIT                       0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT              0x0011c6d0 /* R--4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_TOTAL              15:0 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_UNIQUE            31:16 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT      0x0000 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT            0x0011c6d4 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_TOTAL            15:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_UNIQUE          31:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT    0x0000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS                          0x0011c6d8 /* R--4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_INDEX                          31:0 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_CACHELINE                      15:0 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_ERROR_MASK                    27:16 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_RAM_ID                        31:28 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB2_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CONTROL                          0x0011c6dc /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CONTROL__PRIV_LEVEL_MASK         0x0011c7fc /*       */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR            4:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK       0x1 /* RW--T */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT       0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP       0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR          5:5 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK     0x1 /* RW--T */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT     0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP     0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS                           0x0011c6e0 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA      0:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA    1:1 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA      2:2 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA    3:3 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET                          30:30 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET_CLEAR                      0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET_TASK                       0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_STATUS_RESET_INIT                       0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT              0x0011c6e4 /* R--4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_TOTAL              15:0 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_UNIQUE            31:16 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT      0x0000 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT            0x0011c6e8 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_TOTAL            15:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_UNIQUE          31:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT    0x0000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS                          0x0011c6ec /* R--4R */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_INDEX                          31:0 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_CACHELINE                      15:0 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_ERROR_MASK                    27:16 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_RAM_ID                        31:28 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA            0x0 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_LINK_L1TLB3_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA            0x1 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS                            0x0011c7e0 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA       0:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA     1:1 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA       2:2 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA     3:3 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET                           30:30 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_CLEAR                       0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_TASK                        0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_INIT                        0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT               0x0011c7dc /* R--4R */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL               15:0 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT        0x0000 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE             31:16 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT       0x0000 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT             0x0011c7d8 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL             15:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT      0x0000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE           31:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT     0x0000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS                           0x0011c7d4 /* R--4R */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_INDEX                           31:0 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_CACHELINE                       11:0 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_ERROR_MASK                     27:12 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID                         31:28 /* R-XVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA             0x0 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA             0x1 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUBMMU_GLOBAL_ESR                              0x0011c7d0 /* R--4R */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR                   0:0 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_NOT_PENDING       0x0 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_PENDING           0x1 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR                 1:1 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_NOT_PENDING     0x0 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_PENDING         0x1 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_ERROR_CONTAINMENT_CONTROL                        0x0011c7c0 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_ERROR_CONTAINMENT_CONTROL__PRIV_LEVEL_MASK       0x0011c7fc /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_REISSUE                 0:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_REISSUE_ENABLE          0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_REISSUE_DISABLE         0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_BLACKLIST               1:1 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_BLACKLIST_ENABLE        0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ERROR_CONTAINMENT_CONTROL_ERROR_BLACKLIST_DISABLE       0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER(i)        (0x0011c4e0+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1                    8 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__PRIV_LEVEL_MASK  0x0011c4dc /*       */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL                     31:0 /* RWEUF */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_INIT          0x00000000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_INVALID       0x00000000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB0        0x00000001 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB1        0x00000002 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB2        0x00000004 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB3        0x00000008 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB4        0x00000010 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB5        0x00000020 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB6        0x00000040 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB7        0x00000080 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB8        0x00000100 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB9        0x00000200 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB10       0x00000400 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB11       0x00000800 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB12       0x00001000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB13       0x00002000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB14       0x00004000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_HSHUB15       0x00008000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_ALL_HSHUBS    0x0000001f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_PCIE          0x00000001 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_565MODE       0x80000000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_VAL_464MODE       0x40000000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG                      0x0011c500 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG__PRIV_LEVEL_MASK     0x0011c4dc /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS                        31:0 /* RWEUF */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INVALID          0x00000000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB0      0x00000001 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB1      0x00000002 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB2      0x00000004 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB3      0x00000008 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB4      0x00000010 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB5      0x00000020 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB6      0x00000040 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB7      0x00000080 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB8      0x00000100 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB9      0x00000200 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB10     0x00000400 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB11     0x00000800 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB12     0x00001000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB13     0x00002000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB14     0x00004000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB15     0x00008000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_BOTH_HSHUBS      0x00000003 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ALL_HSHUBS       0x0000001f /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_PCIE             0x00000001 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INIT             0x00000001 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK                        0x0011c508 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION               3:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0        0:0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1        1:1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2        2:2 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3        3:3 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION              7:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "gin_intr_ctrl" /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0        0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1        0xc /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0       4:4 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1       5:5 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2       6:6 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3       7:7 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION                8:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR   0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON     0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION               9:9 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR  0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON    0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL         10:10 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED   0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED   0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL        11:11 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED  0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED  0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE               31:12 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_gin_intr_ctrl_wr_secure" /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL         0xfffff /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE        0x00000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL                                        0x0011c50c /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL__PRIV_LEVEL_MASK                       0x0011c508 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_MESSAGE                                      31:0 /* RWEUF */
#define NV_PFB_HSMMU3_PRI_MMU_INTR_CTRL_MESSAGE_0_INIT                         0xc0000080 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT                                0x0011c510 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_NUM_RANGE_CHECKER              0x00000008 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE                                  3:0 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE_INIT                             0x2 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE                        29:29 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_CLEAR                    0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_SET                      0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_MODE                                30:30 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_ACCESS                           0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_DIRTY                            0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_INIT                             0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE                              31:31 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_FALSE                          0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_TRUE                           0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_INIT                           0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO(i)       (0x0011c514+(i)*8) /* RW-4A */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO__SIZE_1                   8 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_GRANULARITY             3:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_GRANULARITY_INIT        0x5 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL                   31:24 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL_INIT               0x00 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI(i)       (0x0011c518+(i)*8) /* RW-4A */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI__SIZE_1                   8 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL                    31:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL_INIT         0x00000000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL                                     0x0011c558 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL__PRIV_LEVEL_MASK                    0x0011c4d8 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE                     2:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_L2                  0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC              0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_RMW                 0x2 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_POWER               0x3 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_MODE_PCIE                0x4 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA                      4:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA_OFF                  0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_STRONG_BIT_ATOMIC_CYA_ON                   0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE            5:5 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_L2         0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_FOLLOW_SYS_COH 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32                       8:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32_DISABLED              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_32_ENABLED               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64                       9:9 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64_DISABLED              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_FETCH_ADD_64_ENABLED               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32                          10:10 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32_DISABLED                   0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_32_ENABLED                    0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64                          11:11 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64_DISABLED                   0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_SWAP_64_ENABLED                    0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32              12:12 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32_DISABLED       0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_32_ENABLED        0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64              13:13 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64_DISABLED       0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_ATOMICS_CTRL_PCIE_OP_COMPARE_AND_SWAP_64_ENABLED        0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS                                  0x0011c55c /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS__PRIV_LEVEL_MASK                 0x0011c4dc /*       */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_V                                       6:0 /* R--VF */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_COUNT                                   6:0 /* R--VF */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE                             13:8 /* R--VF */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_ZERO                        0x00 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_TWO                         0x02 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_FOUR                        0x04 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_SLICE_MODE_EIGHT                       0x08 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK                            23:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_INIT                        0x00 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER(i)        ((i)+16):((i)+16) /*       */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER__SIZE_1                   8 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_ENABLED                 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_DISABLED                0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_INIT                    0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2                24:24 /* R-EVF */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT             0x0 /* R-E-V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_ENABLED          0x1 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_DISABLED         0x0 /* R---V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM                            25:25 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_INIT                         0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_ENABLED                      0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_C2C_SYSMEM_DISABLED                     0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE                          26:26 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_INIT                       0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_PEER                       0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_SYSMEM                     0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK                      27:27 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK_INIT                   0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK_ENABLED                0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_EGM_APERTURE_CHK_DISABLED               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_NUM_ACTIVE_LTCS_SLICES_PER_LTC                        30:28 /* R--VF */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK       0x0011c6f0 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_SEGMENT_PROTECTION_BITMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK(i)       (0x0011c6f4+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK__SIZE_1                  32 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK__PRIV_LEVEL_MASK 0x0011c6f0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK_BITMAP                 31:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_VMMU_SEGMENT_PROTECTION_BITMASK_BITMAP_INIT      0xffffffff /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK                   0x0011c6a8 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION          3:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0   0:0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1   1:1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2   2:2 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3   3:3 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION         7:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0   0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1   0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0  4:4 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1  5:5 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2  6:6 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3  7:7 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION           8:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION          9:9 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL    10:10 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL   11:11 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE          31:12 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_TEE_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK                     0x0011c6ac /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0     0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1     0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_FSP_GSP_ENABLED_FUSE1 0x0884c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CC_GFID_TEE_STATE_ENABLE(i)              (0x0011c698+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU3_PRI_MMU_CC_GFID_TEE_STATE_ENABLE__SIZE_1                          2 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CC_GFID_TEE_STATE_ENABLE__PRIV_LEVEL_MASK        0x0011c6a8 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CC_GFID_TEE_STATE_ENABLE_BITMASK                       31:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_CC_GFID_TEE_STATE_ENABLE_BITMASK_INIT            0x00000000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE(i)                          (0x0011c6a0+(i)*4) /* RW-4A */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE__SIZE_1                                      2 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE__PRIV_LEVEL_MASK                    0x0011c6ac /*       */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_BITMASK                                   31:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_GFID_DISABLE_BITMASK_INIT                        0x00000000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK                    0x0011c7bc /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION           3:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0    0:0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1    1:1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2    2:2 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3    3:3 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION          7:4 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0   4:4 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1   5:5 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2   6:6 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3   7:7 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION            8:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION           9:9 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL     10:10 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL    11:11 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_ENABLE           31:12 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOTTOM                             0x0011c7b8 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOTTOM__PRIV_LEVEL_MASK            0x0011c7bc /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOTTOM_PER_SLICE                         19:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOTTOM_PER_SLICE_INIT                 0x00000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_MIDDLE                             0x0011c7b4 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_MIDDLE__PRIV_LEVEL_MASK            0x0011c7bc /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE                         19:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_INIT                 0x00000 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE            0x01000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE_LG2        0x0000c /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0                      0x0011c7b0 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0__PRIV_LEVEL_MASK     0x0011c7bc /*       */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL                        10:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_INIT                  0x603 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_0                0x603 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_1                0x423 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_2                0x621 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_3                0x40b /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_4                0x429 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_5                0x4a1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_6                0x681 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_7                0x407 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_8                0x40d /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_9                0x419 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_10               0x431 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_11               0x461 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_12               0x4c1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_13               0x581 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_14               0x701 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CG                                               0x0011c4b0 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_CG_IDLE_CG_DLY_CNT                                      5:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_CG_IDLE_CG_DLY_CNT_HWINIT                              0x02 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CG_IDLE_CG_DLY_CNT__PROD                               0x02 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CG_IDLE_CG_DLY_CNT__MIN_LIMIT                          0x02 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_IDLE_CG_EN                                           6:6 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_CG_IDLE_CG_EN_ENABLED                                   0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CG_IDLE_CG_EN_DISABLED                                  0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CG_IDLE_CG_EN__PROD                                     0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CG_STATE_CG_EN                                          7:7 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_STATE_CG_EN_ENABLED                                  0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_STATE_CG_EN_DISABLED                                 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_STATE_CG_EN__PROD                                    0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_STALL_CG_DLY_CNT                                    13:8 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_STALL_CG_DLY_CNT_HWINIT                             0x02 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_STALL_CG_DLY_CNT__PROD                              0x02 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_STALL_CG_EN                                        14:14 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_CG_STALL_CG_EN_ENABLED                                  0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CG_STALL_CG_EN_DISABLED                                 0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CG_STALL_CG_EN__PROD                                    0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CG_QUIESCENT_CG_EN                                    15:15 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_QUIESCENT_CG_EN_ENABLED                              0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_QUIESCENT_CG_EN_DISABLED                             0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_QUIESCENT_CG_EN__PROD                                0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_WAKEUP_DLY_CNT                                     19:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_CG_WAKEUP_DLY_CNT_HWINIT                                0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CG_WAKEUP_DLY_CNT__PROD                                 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CG_WAKEUP_DLY_CNT__MIN_LIMIT                            0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_THROT_CLK_CNT                                      23:20 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_THROT_CLK_CNT_FULLSPEED                              0xf /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_THROT_CLK_CNT__PROD                                  0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_DI_DT_SKEW_VAL                                     27:24 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_DI_DT_SKEW_VAL_HWINIT                                0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_DI_DT_SKEW_VAL__PROD                                 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_THROT_CLK_EN                                       28:28 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_THROT_CLK_EN_ENABLED                                 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_THROT_CLK_EN_DISABLED                                0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_THROT_CLK_EN__PROD                                   0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_THROT_CLK_SW_OVER                                  29:29 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_THROT_CLK_SW_OVER_EN                                 0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_THROT_CLK_SW_OVER_DIS                                0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_THROT_CLK_SW_OVER__PROD                              0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_PAUSE_CG_EN                                        30:30 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_PAUSE_CG_EN_ENABLED                                  0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_PAUSE_CG_EN_DISABLED                                 0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_PAUSE_CG_EN__PROD                                    0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_HALT_CG_EN                                         31:31 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_HALT_CG_EN_ENABLED                                   0x1 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_HALT_CG_EN_DISABLED                                  0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG_HALT_CG_EN__PROD                                     0x0 /*       */
#define NV_PFB_HSMMU3_PRI_MMU_CG1                                              0x0011c4b4 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_CG1_MONITOR_CG_EN                                       0:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_CG1_MONITOR_CG_EN_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CG1_MONITOR_CG_EN_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CG1_MONITOR_CG_EN__PROD                                 0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CG1_SLCG                                               11:1 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_CG1_SLCG_ENABLED                                      0x000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_CG1_SLCG_DISABLED                                     0x7ff /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_CG1_SLCG__PROD                                        0x000 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PG                                               0x0011c4b8 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_PG_IDLE_BLPG_DLY_CNT                                    7:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PG_IDLE_BLPG_DLY_CNT_HWINIT                            0x0a /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_ELPG_EN_OFFSET_CNT                                  15:8 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PG_ELPG_EN_OFFSET_CNT_HWINIT                           0x0a /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_IDLE_BLPG_EN                                       16:16 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PG_IDLE_BLPG_EN_ENABLED                                 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_IDLE_BLPG_EN_DISABLED                                0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_DIS_EARLY_WUP                                      17:17 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PG_DIS_EARLY_WUP_ENABLED                                0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_DIS_EARLY_WUP_DISABLED                               0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_DEEP_ELPG_EN                                       18:18 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PG_DEEP_ELPG_EN_ENABLED                                 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_DEEP_ELPG_EN_DISABLED                                0x0 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_IDLE_ELPG_EN                                       19:19 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PG_IDLE_ELPG_EN_ENABLED                                 0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_IDLE_ELPG_EN_DISABLED                                0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_DIDT_DELAY                                         23:20 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PG_DIDT_DELAY_HWINIT                                    0xa /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_RESET_DURATION                                     26:24 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PG_RESET_DURATION_HWINIT                                0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_CLAMP_DELAY                                        29:27 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PG_CLAMP_DELAY_HWINIT                                   0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_ZONE_OFF_MASK                                      30:30 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PG_ZONE_OFF_MASK_HWINIT                                 0x1 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_SOFT_GATING_EN                                     31:31 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PG_SOFT_GATING_EN_ENABLED                               0x1 /* RW--V */
#define NV_PFB_HSMMU3_PRI_MMU_PG_SOFT_GATING_EN_DISABLED                              0x0 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PG1                                              0x0011c4c0 /* RW-4R */
#define NV_PFB_HSMMU3_PRI_MMU_PG1_ZONE_SEQ                                           23:0 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PG1_ZONE_SEQ_HWINIT                                0x053977 /* RWE-V */
#define NV_PFB_HSMMU3_PRI_MMU_PG1_ZONE_MASK                                         31:24 /* RWEVF */
#define NV_PFB_HSMMU3_PRI_MMU_PG1_ZONE_MASK_HWINIT                                   0xff /* RWE-V */
#endif // __gr100_dev_fb_h__
