Subject: Re: Interrupts in 1394!

From: "Thomas R. Tewell" <[email-masked]>
Date: Tue, 19 Jan 1999 13:18:53 -0800

> 1.
> There is a Phy interrupt which the OHCI draft says as
> "bit 19 of Interrupt event register (Phy interrupt) :
> The PHY requests an interrupt through a status transfer."
>
> when is this interrupt geenrated and what should be done when this is
generated?

This interrupt is generally ignored...at least we do!?!

> 2.
> Also for bit 25 (CycletooLong) interrupt, what should be done????
> actually when this interrupt occurs, LinkControl.cycleMaster is cleared
and this interrupt
> will be triggered only if LinkControl.cycleMaster is set.
> so i feel probably to handle this interrupt i will have to just set the
cycle master bit back
> to 1....Is it sufficient...
>

If you are indeed the root node, you should reenable the cycle master bit
and that is all you really need to do here.

> 3.
> bit 26 (PhyRegRcvd) interrupt : is this interrupt generated only when i
geenrate a PHY
> register read request???? what are these PHY registers and where are they
residing??? can a
> software access these addresses???
> I just know that we cannot access PHY regsiter 0 since it corresponds to
NODEIDs register.

The PHY is (usually) a separate chip that is connected to the link that
facilitates the actual 1394 signalling on the wire.  PHY chips have a set
of registers that you can access.  Since the Link chip is connected to the
PHY chip(s) on one side and the Link chip is connected to the
computer/device I/O bus on the other side, most Link chips provide a
mechanism for accessing the registers on the PHY chip(s).

The definition of the registers in the PHY depend on the particular PHY
being used, but usually the layout is something like the following:

typedef struct _PHY_REGS {
        BYTE       CablePowerStatus:1;           //Phy Register 0
        BYTE       Root:1;
        BYTE       Physical_ID:6;
        BYTE       GapCount:6;                    //Phy Register 1
        BYTE       InitiateBusReset:1;
        BYTE       RootHoldOff:1;
        BYTE       NumberofPorts:4;                 //Phy Register 2
        BYTE       Reserved:2;
        BYTE       Speed:2;
        BYTE       ReservedA:2;                    //Phy Register 3
        BYTE       Connected1:1;
        BYTE       Child1:1;
        BYTE       BStat1:2;
        BYTE       AStat1:2;
        BYTE       ReservedB:2;                    //Phy Register 4
        BYTE       Connected2:1;
        BYTE       Child2:1;
        BYTE       BStat2:2;
        BYTE       AStat2:2;
        BYTE       ReservedC:2;                    //Phy Register 5
        BYTE       Connected3:1;
        BYTE       Child3:1;
        BYTE       BStat3:2;
        BYTE       AStat3:2;
        BYTE            ManagerCapable:1;              //Phy Register 6
        BYTE            ReservedD:3;
        BYTE            InitiatedReset:1;
        BYTE            CablePowerStat:1;
        BYTE            CablePowerStatusInt:1;
        BYTE            LoopInt:1;
} PHY_REGS, *PPHY_REGS;

You access the PHY through an OHCI Link via the PHY control register in the
OHCI register space at offset 11'h0EC.

To read a PHY register, you set the rdReg bit along with the regAddr
(indicating which PHY register to read (0-6 in the above PHY example) and
wait for rdDone to complete and then lift the data read from the PHY out of
the PHY control register (bits 16-23).

To write a PHY register, you set the wrReg bit along with the regAddr and
the wrData fields.

In either case you will get a Phy interrupt indicating that the PHY wrote
or read to or from the Link chip. In the case of a read you will also get a
PhyRegRcvd interrupt. You can either "poll" the rdDone register or wait for
a PhyRegRcvd interrupt when reading the PHY.  Use the interrupt if you
can't (or don't want to) poll.

Hope this helps,

Thomas "Rick" Tewell
Sequoia Advanced Technologies, Inc.

---

From: Colin Whitby-Strevens <[email-masked]>
Date: Tue, 19 Jan 1999 14:06:12 -0800

Hello Thomas and all,

Note that the PHY register map you describe is the one in Annex J of
IEEE 1394-1995, which is informative.

I personally would strongly recommend that application designers who
are interested in PHY stuff should also study the PHY register map
(Clause 6) of P1394a, which standardizes a much improved (IMHO) PHY
register map. IMHO the sooner that everyone moves to the "normative"
specification the better.

With best wishes

Colin

--
Colin Whitby-Strevens              Email: [email-masked]
Zayante Inc                        Tel: +1 831 461 4948
269, Mt Hermon Road, Suite 201     Fax: +1 831 461 1394
Scotts Valley, CA 95066, USA       Web: www.zayante.com

> -----Original Message-----
> From: IETF IP over 1394 Working Group
> [mailto:[email-masked]]On Behalf Of Thomas R. Tewell
> Sent: 19 January 1999 13:19
> To: [email-masked]
> Subject: Re: Interrupts in 1394!
>
> > 3.